mx25l1005 Macronix International Co., mx25l1005 Datasheet
mx25l1005
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mx25l1005 Summary of contents
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... Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID P/N: PM1238 MX25L1005 1M-BIT [x 1] CMOS SERIAL FLASH 1 REV. 1.9, AUG. 14, 2008 ...
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... All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The MX25L1005 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input ...
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... DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without deselecting the device VCC + 3.3V Power Supply GND Ground P/N: PM1238 MX25L1005 8-LAND USON (2x3mm GND 5 3 VCC HOLD# SCLK SI REV ...
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... BLOCK DIAGRAM Address Generator SI CS# SCLK P/N: PM1238 Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 4 MX25L1005 Output Sense Amplifier Buffer SO REV. 1.9, AUG. 14, 2008 ...
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... DATA PROTECTION The MX25L1005 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1238 Protect level 1Mb 0 (none) None 1 (1 block) Block blocks) All 3 (All) All Hold Condition (standard) 6 MX25L1005 Hold Condition (non-standard) REV. 1.9, AUG. 14, 2008 ...
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... RDP (Page (Deep (Release Program) Power from Deep Down) Power-down) 02 Hex B9 Hex AB Hex AD1 AD2 AD3 7 MX25L1005 READ Fast Read (read data) (fast read data) 03 Hex 0B Hex AD1 AD1 AD2 AD2 AD3 AD3 x n bytes read out CS# goes high ...
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... Table 3. Memory Organization Address Range Bolck Sector 01FFFFh 01F000h 010FFFh 010000h 16 00FFFFh 00F000h 003FFFh 003000h 3 0 002FFFh 002000h 2 001FFFh 1 001000h 000FFFh 000000h 0 P/N: PM1238 . . . . . . 8 MX25L1005 REV. 1.9, AUG. 14, 2008 ...
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... CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1238 shift in MSB 9 MX25L1005 shift out MSB REV. 1.9, AUG. 14, 2008 ...
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... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 11(hex) for MX25L1005. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...
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... Note: 1. See the table "Protected Area Sizes". 2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed 15ms ( multiple of 10,000 cycles, ex for 20,000 cycles) after 10,000 cycles on those bits. P/N: PM1238 MX25L1005 bit 4 bit 3 bit 2 ...
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... BP0. The protected area, which is defined by BP1, BP0 software protected mode (SPM) Note: If SRWD bit=1 but WP# is low impossible to write the Status Register even if the WEL bit has previously been P/N: PM1238 MX25L1005 WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...
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... Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 19) P/N: PM1238 MX25L1005 13 REV. 1.9, AUG. 14, 2008 ...
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... The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 18) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress P/N: PM1238 MX25L1005 14 REV. 1.9, AUG. 14, 2008 ...
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... CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1238 MX25L1005 15 REV. 1.9, AUG. 14, 2008 ...
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... The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: RDID Command manufacturer ID C2 RES Command REMS Command P/N: PM1238 memory type 20 electronic ID 10 manufacturer MX25L1005 memory density 11 device ID 10 REV. 1.9, AUG. 14, 2008 ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1238 MX25L1005 17 REV. 1.9, AUG. 14, 2008 ...
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... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 4. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP 18 MX25L1005 20ns MAX. UNIT CONDITIONS 6 pF VIN = VOUT = 0V REV. 1.9, AUG. 14, 2008 ...
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... Figure 6. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1238 Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 85MHz) 19 MX25L1005 0.5VCC +3.3V REV. 1.9, AUG. 14, 2008 ...
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... V 0.7VCC VCC+0.4 V 0.4 V VCC-0 MX25L1005 TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=85MHz SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz SCLK=0 ...
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... Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1238 0° ° ° ° ° 70° ° ° ° ° C for Commercial grade, VCC = 2.7V ~ 3.6V) 30pF 15pF 21 MX25L1005 Min. Typ. Max. Unit 1KHz 85 MHz ...
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... Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1238 MX25L1005 Min 1.5 22 Max ...
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... Figure 7. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 8. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1238 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 23 MX25L1005 tSHSL tSHCH tCHCL tSHQZ LSB REV. 1.9, AUG. 14, 2008 ...
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... HOLD "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1238 tHLCH tCHHL tCHHH tHLQZ MX25L1005 tHHCH tHHQX tSHWL REV. 1.9, AUG. 14, 2008 ...
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... High-Z SO P/N: PM1238 Command 06 High Command 04 High Manufacturer Identification MSB MSB 25 MX25L1005 Device Identification REV. 1.9, AUG. 14, 2008 ...
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... Status Register MSB High 24-Bit Address MSB 7 MSB 26 MX25L1005 Status Register Out MSB Data Out 1 Data Out REV ...
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... P/N: PM1238 BIT ADDRESS DATA OUT MSB MSB 27 MX25L1005 DATA OUT MSB REV. 1.9, AUG. 14, 2008 ...
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... Address MSB MSB Data Byte MSB 28 MX25L1005 Data Byte Data Byte 256 MSB REV. 1.9, AUG. 14, 2008 ...
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... Figure 20. Block Erase (BE) Sequence (Command 52 or D8) CS# SCLK SI Note: BE command D8(hex). P/N: PM1238 Bit Address Command MSB Command 24 Bit Address MSB 29 MX25L1005 REV. 1.9, AUG. 14, 2008 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 30 MX25L1005 Deep Power-down Mode Sequence RES2 Stand-by Mode REV. 1.9, AUG. 14, 2008 ...
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... Dummy Bytes Manufacturer MSB MSB 31 MX25L1005 Stand-by Mode 47 Device MSB REV. 1.9, AUG. 14, 2008 ...
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... Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) Reset State of the Flash V WI P/N: PM1238 MX25L1005 tVSL Read Command is Device is fully allowed accessible tPUW 32 time REV. 1.9, AUG. 14, 2008 ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1238 tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 33 MX25L1005 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V ...
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... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1238 MX25L1005 Min. TYP. (1) Max. ( ...
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... ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L1005MC-12G 85 MX25L1005MI-12G 85 MX25L1005ZUI-12G 85 P/N: PM1238 OPERATING STANDBY Temperature PACKAGE CURRENT MAX. CURRENT MAX. (mA) (uA MX25L1005 Remark 0~70°C 8-SOP Pb-free (150mil) -40~85°C 8-SOP Pb-free (150mil) -40~85°C 8-USON Pb-free (2x3x0.6mm) REV. 1.9, AUG. 14, 2008 ...
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... PART NAME DESCRIPTION 1005 P/N: PM1238 MX25L1005 OPTION: G: Pb-free SPEED: 12: 85MHz TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M: 150mil 8-SOP ZU: 8-USON (2x3x0.6mm) DENSITY & MODE: 1005: 1Mb TYPE DEVICE: 25: Serial Flash 36 REV. 1.9, AUG. 14, 2008 ...
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... PACKAGE INFORMATION P/N: PM1238 MX25L1005 37 REV. 1.9, AUG. 14, 2008 ...
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... P/N: PM1238 MX25L1005 38 REV. 1.9, AUG. 14, 2008 ...
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... Removed 8-land SON package and order information 1.6 1. Removed 8-USON(4x4mm) package and order information 1.7 1. Added 8-land USON(2x3mm) package and order information 1.8 1. Added 8-land USON (2x3mm) package as "advanced information" P2,3,35,36 2. Removed tCLQV frequency condition 1.9 1. Removed wrong Block Protect Bit, BP2 P/N: PM1238 MX25L1005 Page P1,19,34 P1,20, All P10 P39 P21 P2,3,35,36,39 JAN/22/2008 ...
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... Macronix Europe N.V. Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Singapore Office Macronix Pte. Ltd. 1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 40 MX25L1005 ...