mx25l1005 Macronix International Co., mx25l1005 Datasheet - Page 11

• Manufacturer Part Number: mx25l1005
• Description: 1m-bit [x 1] Cmos Serial Flash
• Manufacturer: Macronix International Co.

Note: 1. See the table "Protected Area Sizes".
P/N: PM1238
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out
on SO (see Figure. 14)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status
register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress.
When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch.
When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write
status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase/write status register instruction.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of
the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect
(BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected
area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions
(only if all Block Protect bits set to 0, the CE instruction can be executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#)
pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal
is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for
execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.
Register Write
register write
1= status
Protect
disable
SRWD
Status
bit 7
2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed
as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.
bit 6
0
bit 5
0
bit 4
0
the level of the level of
protected
(note 1)
11
block
bit 3
BP1
protected
(note 1)
block
bit 2
BP0
MX25L1005
1=write enable 1=write operation
(write enable
0=not write
enable
latch)
WEL
bit 1
(write in progress
REV. 1.9, AUG. 14, 2008
0=not in write
operation
bit 0
WIP
bit)