SI3460-XYY-GM SILABS [Silicon Laboratories], SI3460-XYY-GM Datasheet

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SI3460-XYY-GM

Manufacturer Part Number
SI3460-XYY-GM
Description
IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
I E E E 8 0 2 . 3 a f P S E I
Features
Applications
Description
The Si3460 is a single-port –48 V power management controller for
IEEE 802.3af-compliant Power Sourcing Equipment (PSE). Designed
to minimize system cost and ease of implementation in embedded
PSE endpoint (switches) or midspan (power injector) applications, the
Si3460 operates directly from a 12 or 15 V input supply and integrates
a digital PWM-based dc-dc converter for generating the –48 V PSE
output supply. The IEEE-required Powered Device (PD) detection
feature uses a robust 3-point algorithm to avoid false detection events.
The Si3460's reference design kit also provides full IEEE-compliant
classification and PD disconnect. Intelligent protection circuitry
includes input undervoltage lockout (UVLO), current limiting, and
output short circuit protection. The Si3460 is designed to operate
completely independently of host processor control. An LED status
signal is provided to indicate the port status, including detect, power
good, and output fault event information for use within the host
system. The Si3460 is pin-programmable to support endpoint and
midspan applications, as well as each of the different classification
power
comprehensive reference design kit is available (Si3460-EVB),
including a complete schematic and BOM (Bill-of-Materials) for the dc-
dc converter and PSE functions.
Preliminary Rev. 0.4 11/07
IEEE 802.3af™ compliant PSE and
dc-dc controller
Autonomous operation requires no
host processor interface
Complete reference design
available, including Si3460 controller,
PSE firmware, and schematic:
IEEE 802.3af endpoints and
midspans
Environment A and B PSEs
Embedded PSEs
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
footprint
+15 V isolated supply
PSE output for SELV compatibility
with telephony interfaces
output power (Class 0)
Low-cost BOM with compact PCB
Operates directly from a +12 or
dc-dc controller generates –48 V
Supports up to 15.4 W maximum
levels
specified
by
the
Copyright © 2007 by Silicon Laboratories
IEEE
UNH Interoperability Test Lab test
report available
Extended operating range
(–40 to +85 °C)
11-Pin Quad Flat No-Lead (QFN)
Set-top boxes
FTTH media converters
Cable modem and DSL
gateways
N T E R F A C E A N D
Robust 3-point detection
algorithm eliminates false
detection events
IEEE-compliant classification
IEEE-compliant disconnect
Inrush current control
Short-circuit output fault
protection
LED status signal (detect,
power good, output fault)
Tiny 3 x 3 mm PCB footprint;
Pb-free, RoHS-compliant
802.3af
standard.
A
D C - D C C
250KHZ
CTRL1
CTRL2
GATE
VDD
Top View—Pads on bottom of package
1
2
3
4
5
Pin Assignments
11-pin QFN (3x3 mm)
Si3460
O N T R O L L E R
GND
S i 3 4 6 0
10
9
8
7
6
STATUS
ISENSE
RST
VSENSE
DETA
Si3460

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SI3460-XYY-GM Summary of contents

Page 1

... IEEE 802.3af-compliant Power Sourcing Equipment (PSE). Designed to minimize system cost and ease of implementation in embedded PSE endpoint (switches) or midspan (power injector) applications, the Si3460 operates directly from input supply and integrates a digital PWM-based dc-dc converter for generating the –48 V PSE output supply. The IEEE-required Powered Device (PD) detection feature uses a robust 3-point algorithm to avoid false detection events ...

Page 2

... Si3460 1. Block Diagram OTP Memory Machine RST STATUS 2 PWM DC/DC Osc. Controller: UVLO, Current Limiting, State Short Circuit Protection Control Config. PSE & LED Controller: I/F Detection Classification Disconnect Figure 1. Si3460 Block Diagram Preliminary Rev. 0.4 GATE 250KHZ VSENSE ISENSE CTRL1 CTRL2 DETA ...

Page 3

... Section 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2. Si3460-EVB Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1. Si3460-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. Si3460 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4. Si3460-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1. PSE Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2. DC-DC Converter Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5. Si3460-EVB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1. Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2. Operating Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3. Operating Mode Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 ...

Page 4

... Si3460-EVB Performance Characteristics When implemented according to the recommended external components and layout guidelines for the Si3460- EVB, the Si3460 enables the following performance specifications in single-port PSE applications. Please refer to the Si3460-EVB User’s Guide and schematics for details. Table 1. Selected Electrical Specifications (Si3460-EVB) ...

Page 5

... Table 1. Selected Electrical Specifications (Si3460-EVB) Parameter Symbol Protection and Current Control Overload current threshold I Overload current limit Overload time T Output power at overload P Disconnect current Efficiency System efficiency Test Condition All class levels CUT Output = 100 Ω across V I LIM OUT Output = 100 Ω across V ...

Page 6

... Si3460 3. Si3460 Electrical Specifications The following specifications apply to the Si3460 controller. Refer to Tables and 7, the Si3460-EVB User’s Guide, and schematics for additional details about the electrical specifications of the Si3460-EVB reference design. Table 2. Recommended Operating Conditions* Description Symbol Operating temperature range ...

Page 7

... VDD – 0 – 8 µ Any digital pin 0.7 x VDD Any digital pin Preliminary Rev. 0.4 Si3460 Typ Max Unit — — — — — 0.7 x VDD — — — 0.6 — — 0.1 — 0.4 x VDD — — — ...

Page 8

... Si3460 4. Si3460-EVB Performance Characteristics When implemented in accordance with the recommended external components and layout guidelines, the Si3460 controller enables the following typical performance characteristics in single-port PSE applications. Refer to the Si3460-EVB applications note, schematics, and user's guide for more details. Table 5. PSE Performance Characteristics ...

Page 9

... PSE Timing Characteristics When implemented in accordance with the recommended external components and layout guidelines, the Si3460 controller enables the following typical performance characteristics in single-port PSE applications. Refer to the Si3460-EVB applications note, schematics, and user's guide for more details. Description Symbol Endpoint detection delay ...

Page 10

... Si3460 4.2. DC-DC Converter Performance Characteristics The dc-dc converter utilizes a digital control loop architecture operating at 250 kHz. The complete converter is comprised of the Si3460 controller and the external components in the Si3460-EVB schematics. The performance specifications in Table 7 are typical for the Si3460-EVB reference design. Parameter Symbol ...

Page 11

... Si3460-EVB reference design. Refer to the Si3460-EVB User’s Guide and schematics for descriptions in the following sections. 5.1. Reset State At powerup or if reset is held low, the Si3460 inactive state with the PWM turned off (the switcher FET, M1, is off) and the pass FET, M2, is off. 5.2. Operating Mode Configuration At powerup, the Si3460 reads the voltage on the STATUS pin, which is set by a resistor divider from V ground ...

Page 12

... The STATUS LED is continuously lit when power is applied. If the output power exceeds the level determined by the initial voltage of the STATUS pin, the Si3460 will declare an error and shut down the port, flashing the LED rapidly to indicate the error (for either two seconds or until reset as determined by the initial voltage on the STATUS pin) ...

Page 13

... Si3460 will declare a PD disconnect, and the dc-dc converter clock (250 kHz) and FET M1 will be turned off. As set by the initial voltage on the STATUS pin, the Si3460 will then automatically resume the detection process after 250 ms for "Endpoint mode" and two seconds for "Midspan mode." The difference in these two backoff timings is specified by the IEE 802 ...

Page 14

... The input power supply should be rated for at least 25% higher power level than the output power level chosen. This is primarily to account for the 75 to 80% nominal efficiency performance of the Si3460-EVB reference design. For example, to support a Class 0 PSE, for example, the input supply should be capable of supplying 19.25 W (15 ...

Page 15

... Si3460 Pin Descriptions Si3460 pin functionality is described in Table 10. Note that the information applies to the Si3460 device pins, while the Si3460-EVB User’s Guide describes the inputs and outputs of the evaluation system. The electrical characteristics of the Si3460-EVB are summarized in Table 1, “Si3460-EVB Performance Characteristics Summary,” ...

Page 16

... GND GND 16 Pin Function Active low reset input. When low (to GND), places the Si3460 device into an inactive state. The dc-dc converter is disabled. When pulled high, the device begins the detection process sequence. The dc-dc begins to function after a valid R ture is detected, indicating a valid PD has been detected. ...

Page 17

... Ordering Guide Ordering Part Number Single-port PSE controller for embed- ded applications; extended tempera- Si3460-XYY-GM ture range Single-port PSE evaluation board and Si3460-EVB reference design Notes: 1. “X” denotes silicon revision. “YY” denotes firmware revision. 2. Add “R” to part number for tape and reel option (e.g. Si3460-X-GMR). ...

Page 18

... Si3460 9. Package Outline: 11-Pin QFN Figure 5 illustrates the package details for the Si3460. Table 11 lists the values for the dimensions shown in the illustration. The Si3460 is packaged in an industry-standard, 3x3 mm, RoHS-compliant, Pb-free, 11-pin QFN package. Bottom View Side E View ...

Page 19

... Solder Paste Mask 0.10 mm 0.35 mm 0.50 mm 0. 0.50 mm 0.35 mm 0. 0.60 mm 0. Figure 6. Solder Paste Mask Preliminary Rev. 0.4 Si3460 0. ...

Page 20

... Si3460 9.2. PCB Landing Pattern 0.10 mm 0.35 mm 0.50 mm 0. Figure 7. Typical QFN-11 Landing Diagram 0. Preliminary Rev. 0.4 ...

Page 21

... Line 1 is the part number; line 2 is the lot code, and line 3 is the date code. The Lot ID Code on the top side of the device package can be used for decoding device revision information. On Si3460 devices, the silicon revision letter is the first letter of the Lot ID Code on the second line of the device mark. Figure 8 shows how to find the Lot ID Code on the top side of the device package for production devices ...

Page 22

... Si3460 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: PoEInfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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