sed1374 ETC-unknow, sed1374 Datasheet - Page 309

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Epson Research and Development
Vancouver Design Center
4 VR4102 to SED1374 Interface
4.1 Hardware Description
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
NEC V
DATA[15:0]
ADD[15:0]
RSTOUT
LCDRDY
BUSCLK
LCDCS#
R
4102
SHB#
WR#
RD#
Figure 4-1: Typical Implementation of VR4102 to SED1374 Interface
The NEC V
controller by providing the internal address decoding and control signals necessary. By
using the Generic # 2 interface, only one inverter is required to change the polarity of the
system reset signal to active low. A pull-up resistor is attached to WAIT# to speed up its
rise time when terminating a cycle.
The following diagram shows a typical implementation of the VR4102 to SED1374
interface.
R
4102 Microprocessor is specifically designed to support an external LCD
Pull-up
Vcc
Vcc
RD#
WE1#
RD/WR#
CS#
WAIT#
RESET#
AB[15:0]
DB[15:0]
BUSCLK
BS#
WE0#
SED1374
X26A-G-008-04
SED1374
Page 13

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