sed1374 ETC-unknow, sed1374 Datasheet - Page 385

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

EPSON Research and Development
Vancouver Design Center
3.2 IT8368E Configuration
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
Note
The “Generic #1” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1374 clock frequencies.
The SED1374 also has internal clock dividers providing additional flexibility.
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E must have both “Fix
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide
control signals needed by the SED1374 host bus interface, and a 16M byte portion of the system PC
Card attribute and IO space is allocated to address the SED1374. When accessing the SED1374 the
associated card-side signals are disabled in order to avoid any conflicts.
For mapping details, refer to section 3.3: “Memory Mapping and Aliasing.” For connection details
see Figure 3-1: “SED1374 to PR31500/PR31700 Connection Using an IT8368E,” on page 10. For
further information on the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip Specification.
When a second IT8368E is used, that circuit should not be set in VGA mode.
X26A-G-012-01
SED1374
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