SI5010-GM SILABS [Silicon Laboratories], SI5010-GM Datasheet
SI5010-GM
Related parts for SI5010-GM
SI5010-GM Summary of contents
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... SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Board level serial links Description The Si5010 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data ® rates. DSPLL ...
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... Si5010 2 Rev. 1.3 ...
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... Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.8. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8. Package Outline: Si5010-BM/ 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Rev. 1.3 Si5010 Page 3 ...
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... Si5010 1. Detailed Block Diagram DIN+ DIN+ Phase Phase Phase Detector Detector Detector DIN– REFCLK+ REFCLK+ REFCLK– RATESEL REXT Bias Bias Bias G eneration G eneration G eneration 4 CLK A/D VCO DSP Divider n Lock Detector Calibration Rev. 1.3 DOUT+ Retim e Retim e Retim e DOUT– c CLKOUT+ c CLKOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "3. Typical Application Schematic" on page 9. ...
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... Si5010 Table 2. DC Characteristics (V = 2.5 V ±5 –40°C to 85° Parameter Supply Current OC-12 OC-3 Power Dissipation OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Single Ended Input Voltage (DIN, REFCLK) Differential Input Voltage Swing* (DIN, REFCLK) Input Impedance (DIN, REFCLK) Differential Output Voltage Swing ...
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... GEN(PP) J OC-12 Mode BW OC-3 Mode J f < 2 MHz P T After falling edge of AQ PWRDN/CAL From the return of valid data C DUTY C TOL LOL LOCK Rev. 1.3 Si5010 Min Typ Max Unit .15 — 666 MHz — 80 110 ps 835 880 930 ps 4040 4090 4140 ps — ...
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... Si5010 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Typical Application Schematic High-Speed Serial Input System Reference Clock LVTTL Control Inputs Loss-of-Lock Indicator 2 DIN+ DIN– Si5010 REFCLK+ CLKOUT+ REFCLK– CLKOUT– 0.1 µF 10 kΩ VDD (1%) 2200 Rev. 1.3 Si5010 DOUT+ Recovered Data DOUT– Recovered Clock 9 ...
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... When REFCLK is absent, the LOL alarm will always be asserted when it has been determined that no activity exists on REFCLK, indicating the lock status of the PLL is unknown. Additionally, the Si5010 uses the reference clock to center the VCO operating frequency so that clock and data can be recovered from the input data stream. The VCO operates at an integer multiple of the REFCLK frequency. (See “ ...
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... Note: LOL is not asserted when the device is in the power- down state. 4.8. Device Grounding The Si5010 uses the GND pad on the bottom of the 20-pin QFN package for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. ...
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... Si5010 4.10. Differential Input Circuitry The Si5010 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6 ...
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... Differential Output Circuitry The Si5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. 100 Ξ ...
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... VDD Top View Figure 10. Si5010 Pin Configuration Table 8. Si5010 Pin Descriptions I/O Signal Level External Bias Resistor. This resistor is used by onboard circuitry to estab- lish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resis- tor. Supply Voltage. ...
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... Table 8. Si5010 Pin Descriptions (Continued) Pin # Pin Name I/O 12 DOUT– DOUT+ 15 PWRDN/CAL I 16 CLKOUT– CLKOUT+ 19 RATESEL Signal Level Differential Data Output. CML The data output signal is a retimed version of the data recovered from the signal present on DIN phase aligned with CLKOUT and is updated on the rising edge of CLKOUT ...
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... Si5010 6. Ordering Guide Part Number Si5010-BM Si5010-GM 7. Top Mark Silicon Labs Part Number Si5010-BM Si5010-GM 16 Package Temperature 20-pin QFN – °C 20-pin QFN – °C Die Revision (R) Part Designator ( Rev. 1.3 Lead Finish 85/15 Pb/Sn Matte Sn (Pb-free ...
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... Package Outline: Si5010-BM/GM Figure 11 illustrates the package details for the Si5010-BM/GM. Table 9 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 11. 20-pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 A2 — ...
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... Si5010 9. 4x4 mm 20L QFN Recommended PCB Layout See Note 8 Symbol A Pad Row/Column Width/Length D Thermal Pad Width/Height e Pad Pitch G Pad Row/Column Separation R Pad Radius X Pad Width Y Pad Length Z Pad Row/Column Extents Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad ...
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... L OCUMENT HANGE IST Revision 1.0 to Revision 1.1 Added "7. Top Mark" on page 16. Updated “8. Package Outline: Si5010-BM” on page 17. Added "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. Revision 1.1 to Revision 1.2 Made minor note corrections to "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. ...
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... Si5010 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...