k4d553238f-jc Samsung Semiconductor, Inc., k4d553238f-jc Datasheet - Page 8

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k4d553238f-jc

Manufacturer Part Number
k4d553238f-jc
Description
256mbit Gddr Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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MODE REGISTER SET(MRS)
latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make GDDR SDRAM
useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register
must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS
and WE(The GDDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The
state of address pins A
register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks are
in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
addressing mode uses A
used for DLL reset. A
for various burst length, addressing modes and CAS latencies.
* RFU(Reserved for future use)
The mode register stores the data for controlling the various operating modes of GDDR SDRAM. It programs CAS
RFU
K4D553238F-JC
BA
should stay "0" during MRS
cycle.
MRS Cycle
BA
Command
0
1
CK, CK
1
0
BA
0
0
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
EMRS
A
MRS
n
DLL
~ A
A
A
0
1
11
8
0
7,
0
A
DLL Reset
NOP
8
~ A
RFU
3
A
, BA
, CAS latency(read latency from column address) uses A
t
10
Yes
No
RP
11
0
0
is required to issue MRS command.
and BA
and BA
Precharge
All Banks
A
9
0
1
1
, BA
DLL
must be set to low for normal MRS operation. Refer to the table for specific codes
CAS Latency
Test Mode
A
8
A
0
0
0
0
1
1
1
1
A
1
0
1
6
7
NOP
in the same cycle as CS, RAS, CAS and WE going low is written in the mode
TM
A
0
0
1
1
0
0
1
1
A
2
5
7
Normal
Test
t
mode
RP
A
0
1
0
1
0
1
0
1
NOP
4
A
6
CAS Latency
- 8 -
Latency
3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A
3
4
5
MRS
Burst Type
A
0
1
3
4
A
4
Sequential
Burst Length
Interleave
t
MRD
NOP
A
0
0
0
0
1
1
1
1
Type
2
=2 t
BT
A
5
3
CK
A
0
0
1
1
0
0
1
1
4
1
~ A
Command
256M GDDR SDRAM
A
Any
A
0
1
0
1
0
1
0
1
6
2
. A
Burst Length
0
6
7
Sequential
is used for test mode. A
A
Reserve
Reserve
Reserve
Reserve
Reserve
1
NOP
Rev 1.0 (Mar. 2004)
2
4
8
Burst Type
7
A
0
NOP
Interleave
Mode Register
Address Bus
Reserve
Reserve
Reserve
Reserve
Reserve
8
2
4
8
0
~ A
8
2
is
,

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