k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 6

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QF-GC
~ WDQS3
BA0, BA1
~ RDQS3
CAS, WE
A0 ~ A11
WDQS0
NC/RFU
Symbol
~ DQ31
RDQS0
CK, CK
~DM3
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
V
V
RAS,
V
DM0
CKE
DQ0
RES
V
V
CS
ZQ
DDQ
SSQ
REF
DD
SS
Reference Resistor connection pin for On-die termination.
Supply
Supply
Supply
Supply
Supply
Output
Output
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive
edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buff-
ers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all
banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and
exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection
on systems with multiple banks. CS is considered part of the command code.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM
pins are input only, the DM loading matches the DQ and DQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is
being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8
is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW)
or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address
inputs also provide the op-code during Mode Register Set commands.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto
precharge.
Data Input/ Output: Bi-directional data bus.
READ Data Strobe: Output with read data. RDQS is edge-aligned with read data.
WRITE Data Strobe: Input with write data. WDQS is center-aligned to the input data.
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.0V ± 0.1V
DQ Ground
Power Supply: 2.0V ± 0.1V
Ground
Reference voltage: 0.7*VDDQ ,
2 Pins : (M,2) for Data input , (M,13) for CMD and ADDRESS
The value of Resistor = 240 Ω
Reset pin: RESET pin is a VDDQ CMOS input
- 6 -
Function
256M GDDR3 SDRAM
Rev 1.7 (Jan. 2005)