msm80c85ahrs Oki Semiconductor, msm80c85ahrs Datasheet

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msm80c85ahrs

Manufacturer Part Number
msm80c85ahrs
Description
8-bit Cmos Microprocessor
Manufacturer
Oki Semiconductor
Datasheet

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E2O0009-27-X2
This version: Jan. 1998
¡ Semiconductor
¡ Semiconductor
MSM80C85AHRS/GS/JS
Previous version: Aug. 1996
MSM80C85AHRS/GS/JS
8-Bit CMOS MICROPROCESSOR
GENRAL DESCRIPTION
The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate
C-MOS technology and compatible with MSM80C85A.
It is designed with higher processing speed (max.5 MHz) and lower power consumption
compared with MSM80C85A and power down mode is provided, thereby offering a high level
of system integration.
The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-
bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory
product allows a direct interface with the MSM80C85AH.
FEATURES
• Power down mode (HALT-HOLD)
• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85 C, Operating Temperature
• Compatible with MSM80C85A
• 0.8 ms instruction Cycle (V
= 5V)
CC
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System
Control
• Bug operation in MSM80C85AH is fixed
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)
1/29

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msm80c85ahrs Summary of contents

Page 1

... Decimal, Binary and Double Precision Arithmetic • Addressing Capability to 64K Bytes of Memory • TTL Compatible • 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS) • 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS) • 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K) This version: Jan. 1998 MSM80C85AHRS/GS/JS Previous version: Aug ...

Page 2

... Arithmetic Decoder Logic Unit D REG (8) And ALU(8) Machine H REG (8) Cycle Encoding Stack Pointer (16) Program Counter (16) Incrementer/Decrementer Address Latch (16) DMA Reset Address Buffer (8) Address Bus MSM80C85AHRS/GS/JS SOD C REG (8) E REG (8) C REG (8) Register Array Data/Address Buffer ( Address/Data Bus ...

Page 3

... Semiconductor PIN CONFIGURATION (TOP VIEW) 44 pin Plastic QFP TRAP 1 RST7.5 2 RST6.5 3 RST5.5 4 INTR 5 INTA MSM80C85AHRS/GS/JS 40 pin Plastic DIP RESET OUT 4 37 SOD 5 36 SID 6 35 TRAP 34 RST7 RST6.5 32 RST5 ...

Page 4

... Table 1.) Power down mode is reset by input of TRAP. Function IO/M S States S 1 Memory write 1 1 Memory read . 0 I/O write . ¥ I/O read . ¥ Opcode fetch and S become valid at the beginning MSM80C85AHRS/GS/JS States 0 1 Interrupt Acknowledge 0 Halt = 3-state Hold (high impedance) ¥ Reset ¥ = unspecified ¥ 4/29 ...

Page 5

... INTR 5 Notes: (1) The processor pushes the PC on the stack before branching to the indicated address. (2) The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged. MSM80C85AHRS/GS/JS Function 1 Type Trigger 24H Rising edge and high level unit sampled. 3CH Rising edge (latched). ...

Page 6

... INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive. Register 8-bits 16-bit address 8-bit ¥ 16-bits ¥ 3 16-bit address 5 flags (8-bit space and IO/M signals for bus control. An Interrupt 0 1 MSM80C85AHRS/GS/JS Contents 6/29 ...

Page 7

... The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data. External TRAP Interrupt Request RESET IN Figure 3 Trap and RESET IN Circuit Inside the MSM80C85AH TRAP RESET Schmitt Trigger + CLK Q D F/F Clear Internal TRAP F.F TRAP Acknowledge MSM80C85AHRS/GS/JS TRAP Interrupt Request 7/29 ...

Page 8

... Figure 4 Clock Driver Circuits INPUTS , X and ground. These capacitors are required through the driving circuit MHz Input Frequency External Clock Drive Circuit V > 0 High time > Low time > MSM80C85AHRS/GS/ Left Floating 2 8/29 ...

Page 9

... Machine Cycle Opcode Fetch (OF) Memory Read (MR) Memory Write (MW) I/O Read (IOR) I/O Write (IOW) Acknowledge of INTR (INA) Bus Idle (BI): DAD ACK. OF RST, TRAP HALT MSM80C85AHRS/GS/JS ) and the three control signals (RD, WR,and , state, at the outset of each machine cycle. Control 1 Status RD IO ...

Page 10

... TS ¥ ( ¥ (PC+1) H (PC+1) L1 Data from Memory (I/O Port Address) 10 (Read) MSM80C85AHRS/GS/JS Control INTA ALE ( ¥ ¥ 0 ¥ ¥ 0 ¥ ¥ ...

Page 11

... In this case, the POWER DOWN mode can be released either by means of the RESET pin or by releasing the HOLD status by means of HOLD pin. Released by using pins RESET and INTERRUPT (not by pin HOLD) Released by using RESET and HOLD pins (not by interrupt pins) MSM80C85AHRS/GS/JS 11/29 ...

Page 12

... CLK (OUT) ALE HOLD HLDA Run CPU MODE Figure 8 Started and Released by HOLD HLT Address Power Down HLT Power Down T HOLD Power Down MSM80C85AHRS/GS/ RESET 1 2 Address Run Run RUN ...

Page 13

... IH V –0.3 — ILR V 3.0 — IHR Conditions = 2 –2 –100 mA £ 4 5 £ –40°C - +85°C OUT CC = 200 ns cyc = reset L = 200 ns cyc = power L MSM80C85AHRS/GS/JS Units °C 1.0 W Unit V °C Unit Max. 5.5 V +85 ° +0.3 ...

Page 14

... Control Trailing Edge to Leading Edge of Next Control Data Hold Time After RD INTA (7) READY Hold Time READY Setup Time to Leading Edge of CLK Data Valid After Trailing Edge of WR LEADING Edge Data Vaild MSM80C85AHRS/GS/JS (Ta = –40°C ~ 85° Symbol Condition Min. ...

Page 15

... AC t — — — — LDR Note equal to the total WAIT states CYC MSM80C85AHRS/GS/JS and S 0 =200 ns C =150 pF CYC L =150 pF use the following correction factors: L < 150 pF : –0.10ns/pF L £ 200 pF : +0.30ns/ 2.2 Test Points ...

Page 16

... AD Address AFR t LDR LCK Address t LDW Address Data Out WDL MSM80C85AHRS/GS/ RAE t RDH Data 16/29 ...

Page 17

... Note: READY must remain stable during setup and hold times. Figure 7 MSM80C85AH Bus Timing, With and Without Wait HOLD OPERATION T 2 CLK HOLD t HDS HLDA BUS (Address, Controls) Figure 8 MSM80C85AH Hold Timing MSM80C85AHRS/GS/ WAIT t AD Data In t LDR ...

Page 18

... A 8-15 AD 0-7 ALE RD INTA INTR t t INS INH HOLD t HDS HLDA NOTE: (1) IO/M is also floating during this time Call Inst Bus Floating t HDH t t HACK HABF Figure 9 MSM80C85AH Interrupt and Hold Timing MSM80C85AHRS/GS/ HOLD 1 2 (1) t HABE 18/29 ...

Page 19

... H & program counter CALL CALL Call unconditional CC Call on carry CNC Call on no carry CZ Call on zero CNZ Call on no zero CP Call on positive CM Call on minus CPE Call on parity even CPO Call on parity odd MSM80C85AHRS/GS/JS Instruction Code ( ...

Page 20

... Add stack pointer to H & L SUBTRACT SUB r Subtract register from A SBB r Subtract register from A with borrow SUB M Subtract memory from A SBB M Subtract memory from A with borrow SUI Subtract immediate from A SBI Subtract immediate from A with borrow MSM80C85AHRS/GS/JS Instruction Code ( ...

Page 21

... When power is turned on, the output level (SOD etc.) is unknown before the equipment is reset. (3) Bug of MSM80C85A–2 at power down has fixed. (4) Because Spike Noise would be output on HLDA, RESET OUT and CLK pins, depending on the customers condition of usage; please take into account this issue at System Board design. MSM80C85AHRS/GS/JS Instruction Code ( ...

Page 22

... IE (Interrupt Enable Flag): When interrupt is Enable, "1" is read out. M7.5 (Mask RST7.5): When RST7.5 interrupt is masked, "1" is read out. M6.5 (Mask RST6.5): When RST6.5 interrupt is masked, "1" is read out. M5.5 (Mask RST5.5): When RST5.5 interrupt is masked ,"1" is read out. MSM80C85AHRS/GS/ ...

Page 23

... High-speed device (New) M80C85AH M80C86A-10 M80C88A-10 M82C84A-2 M81C55-5 M82C37B-5 M82C51A-2 M82C53-2 M82C55A-2 Remarks Low-speed device (Old) M80C85A/M80C85A-2 8bit MPU 16bit MPU M80C86A/M80C86A-2 8bit MPU M80C88A/M80C88A-2 Clock generator M82C84A/M82C84A-5 RAM.I/O, timer M81C55 DMA controller M82C37A/M82C37A-5 USART M82C51A Timer M82C53-5 PPI M82C55A-5 MSM80C85AHRS/GS/JS 23/29 ...

Page 24

... V minimum (-400 mA) 4.2 V minimum (-40 mA maximum (@5 MHz maximum (@5 MHz) ranges the MSM80C85AH contain those of the MSM80C85A/ OH MSM80C85AHRS/GS/JS MSM80C85AH 2mSi-CMOS MSM80C85AH Provided (The malfunction has been removed.) The contents of data in T3 cycle are retained (for low power consumption). MSM80C85AH MSM80C85AH 0 ...

Page 25

... RD 300 ns t Min RV 400 ns t Min WD 100 ns t Max WDL 40 ns Notes: The italicized or underlined values indicate that they are different from those of the MSM80C85AH. MSM80C85AHRS/GS/JS MSM80C85A-2 MSM80C85AH 200 ns 200 115 ns 115 ns 115 ns 115 ns 330 ns ...

Page 26

... Especially, HLDA, RESOUT, and CLKOUT pins must be evaluated. 2) The MSM80C85AH basically satisfies the characteristics of the MSM80C85A-2 and the MSM80C85A, but their timings are a little different, Therefore, when critical timing is required in designing recommended to evaluate operating margins at various temperatures and voltages. MSM80C85AHRS/GS/JS 26/29 ...

Page 27

... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM80C85AHRS/GS/JS (Unit : mm) Package material Epoxy resin ...

Page 28

... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM80C85AHRS/GS/JS (Unit : mm) Package material Epoxy resin ...

Page 29

... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM80C85AHRS/GS/JS (Unit : mm) Package material Epoxy resin ...

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