com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 75

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

A0-A19
nTOPL
IOCHRDY
nMEMR
nPROM **
BALE
*** For Revision D devices, if BALE is tied high, then Address must be held for 20 nsec
**
*
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched
Address Mode.
All PROM accesses are 8-bit only, ROM should use nMEMR as nOE signal and PROM
as nCS.
after nMEMR Low.
nMEMR Low to nTOPL Low
nMEMR High to nTOPL High
nMEMR Low to IOCHRDY Low
Address Set Up to BALE Low *
Address Hold after BALE Low *
Address, Set Up to nMEMR Low
nMEMR Low to nPROM Low
IOCHRDY Low Pulse Width
nMEMR High to nPROM HIgh
nMEMR High to BALE High (Next Address)
Modified Version of Page 54 for Rev. D COM90C66 Only.
Parameter
FIGURE 19 - READ PROM CYCLE
t1
t3
VALID
t4
t6
t2
t5
75
t2
***
t7
min
100
20
20
50
30
0
0
0
0
0
typ
max
165
25
30
20
15
30
t8
t10
t9
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS