ax88196 ASIX Electronics Corporation, ax88196 Datasheet - Page 19

• Manufacturer Part Number: ax88196
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Mac Controller With Embedded Memory
• Manufacturer: ASIX Electronics Corporation

4.3 Interrupt mask register (IMR) Offset 0FH (Write)
4.4 Data Configuration Register (DCR) Offset 0EH (Write)
4.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
FIELD
FIELD
6:2
4:3
2:1
7
6
5
4
3
2
1
0
7
1
0
7
6
5
0
AX88196
LB1,LB0 Encoded Loop-back Control
NAME
NAME
NAME
OVWE Overwrite Interrupt Enable. Default “low” disabled.
RDCE DMA Complete Interrupt Enable. Default “low” disabled.
CNTE
TXEE
RXEE
RDCR Remote DMA always completed
PTXE
PRXE
WTS
BOS
FDU
RLO
CRC
PD
-
-
-
Reserved
Counter Overflow Interrupt Enable. Default “low” disabled.
Transmit Error Interrupt Enable. Default “low” disabled.
Receive Error Interrupt Enable. Default “low” disabled.
Packet Transmitted Interrupt Enable. Default “low” disabled.
Packet Received Interrupt Enable. Default “low” disabled.
Reserved
Byte Order Select
Word Transfer Select
Full Duplex :
Pad Disable
Retry of late collision
Reserved
Mode 0
Mode 1
Mode 2
Inhibit CRC
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80186).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(MC68K)
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
This bit indicates the current media mode is Full Duplex or not.
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
These encoded configuration bits set the type of loop-back that is to be performed.
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
0 : Half duplex
1 : Full duplex
LB1 LB0
1
0
0
0
0
1
Internel NIC loop-back
PHYcevisor loop-back
Normal operation
Local CPU BUS MAC Controller
19
DESCRIPTION
DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION