ch7028b Chrontel, ch7028b Datasheet - Page 12

• Manufacturer Part Number: ch7028b
• Description: Chrontel Ch7028b Sdtv Encoder
• Manufacturer: Chrontel

CHRONTEL
(Note: VSYNC pulse of CPU/MEMERY interface is not necessary for each input frame, it is required to appear at least
one time at any input frame blank period.)
2.1.3 Input Data Voltage
The voltage level of input pins D[17:0], H, V, DE, are from 0 to VDDIO. These pins support two input mode, one is
CMOS mode, and the other is pseudo differential mode. The default is CMOS mode with CMOS level on these pins.
When control bit DIFFEN is high, the input is pseudo differential mode that uses a reference voltage (VREF) to
compare with input voltage and decide input logic value. The VREF value can be 80%, 70%, 60% and 50% of VDDIO
value, referring to VRTM[1:0]. The pseudo differential mode can accept the wide range of the input voltage level from
1.2v to 3.3v, while the CMOS mode can accept 1.8v to 3.3v input voltage.
2.1.4 Input Data Format
The following table indicates the supported input data format by CH7028B.
12
CSB
VSYNC
WEB
D[17:0]
D[15:0]
D[7:0]
Line
Vsync
Hsync
DE
VW
Figure 7: CPU/MEMERY Interface Timing
…
Figure 6: Vertical Input Timing
VT
VA
209-1000-001
…
Rev. 1.1,
VO
CH7028B
08/21/2008