UPD16448AN NEC [NEC], UPD16448AN Datasheet
UPD16448AN
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UPD16448AN Summary of contents
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SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV) PD16448A is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and two ...
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BLOCK DIAGRAM 3 CLI R/L STHR INH RESET C 1 Multi plexer C 3 MP/TH ..................................................................................................... MP/1 SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT VIDEO LINE Swa1 Swa2 2 240-bit shift register 240-bit ...
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PIN CONFIGRATION ( PD16448A N-xxx DD2 V DD1 STHL MP/TH MP/1.5 R/L RESET INH CLI 1 CLI 2 CLI 3 TEST STHR V SS1 V SS3 V SS2 This figure does not spesify ...
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PIN DESCRIPTION Symbol Name Video signal input Video signal output 1 240 STHR Cascade I/O STHL CLI Shift clock input 1 CLI 2 CLI 3 INH Inhibit input RESET Reset input ...
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FUNCTION DESCRIPTION 2.1 Multiplexer Circuit This circuit selects RGB video signals input to the C crystal panel, and outputs the signals to the H Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the ...
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Timing chart of vertical stripe array RESET INH 240 Un- sampling defined input data Output Undefined 239 Un- sampling defined input data ...
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Single-side delta array mode (MP/ MP/1 Relation between video signals C Line No. (number of RESET INH INHs Pixel arrangement of single-side ...
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Timing chart of single-side delta array RESET INH 240 Un- sampling Undefined defined input data Output 239 Un- sampling Undefined defined input data Output Undefined 238 Un- sampling ...
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Double-side delta array mode (MP/ MP/1 Because the pad pitch of the PD16448A is designed so that the IC is mounted on one side, the output pitch must be expanded on the TCP if the ...
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Timing chart of double-side delta array RESET INH 240 Un- sampling Undefined defined input data Output 239 Un- sampling Undefined defined input data Output Undefined 238 Un- sampling ...
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Mosaic array mode (MP/ MP/1 Relation between video signals C Line No. (number of RESET INH INHs ...
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Timing chart of mosaic array RESET INH 240 Un- sampling Undefined defined input data Output 239 Un- sampling Undefined defined input data Output Undefined 238 Un- sampling Undefined ...
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Relation between Shift Clock CLI (1) Simultaneous sampling (( ) indicates the case of left shift.) CLI 1 STHR (STHL) SHP (SHP ) 1 240 SHP (SHP ) 2 239 SHP (SHP ) 3 238 SHP (SHP ) 4 ...
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Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and change at the rising and falling ...
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Write Operation Timing The sampled video signals are written to the LCD panel by output currents I dynamic range is 4 5.0 V). MIN DD2 While INH = H, do not stop shift clocks CLI ...
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Use] 1. Turn ON power to V DD1 destruction due to latchup, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. This IC is designed to input successive signals ...
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CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (T Parameter Symbol Logic supply voltage Driver supply voltage Logic input voltage Video input voltage Logic output voltage Driver output voltage Driver output current Operating temperature range Storage temperature range Caution If the absolute maximum ...
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ELECTRICAL CHARACTERISTICS (T = - 3 DD1 Parameter Symbol Maximum video signal output voltage V Minimum video signal output voltage V Logic output voltage, high V Logic output voltage, low ...
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SWITCHING CHARACTERISTICS (T A Parameter Symbol Start pulse propagation delay time t PHL t PLH Maximum clock frequency 1 f max. 1 Maximum clock frequency 2 f max. 2 Logic input capacitance C STHL, STHR input capacitance C Video input ...
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SWITCHING CHARACTERISTIC WAVE (simultaneous/successive sampling) Start Pulse Input Timing PW CLI1 CLI SETUP STHR 50 % (STHL) SHP 1 (SHP ) 240 Start Pulse Output Timing CLI PLH STHL (STHR) Remark The ...
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RESET INH Pulse Timing CLI 1 PW RES 50% 50% RESET INH t R-I 50 IIHOLD ISETUP 50% PW INH PD16448A 50% 21 ...
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RECOMMENDED CONDITIONS FOR INSTALLATION This product should be installed under the following recommended conditions. representatives for installation under conditions other than those recommended. Installation Condition Installation Method Thermocompression Soldering bonding ACF (sheet type adhesive agent) Caution For installation conditions ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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REFERENCE NEC Semiconductor Device Reliability/Quality Control System Quality Grade on NEC Semiconductor Devices The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied ...