UPD16448AN NEC [NEC], UPD16448AN Datasheet - Page 16

• Manufacturer Part Number: UPD16448AN
• Description: SOURCE DRIVER FOR 240-OUTPUT TFT-LCD NAVIGATION, AUTOMOBILE LCD-TV
• Manufacturer: NEC [NEC]

[Cautions on Use]
16
1.
2.
3.
4.
5.
6.
7.
STHR (STHL)
This IC is designed to input successive signals such as chrome signals. The input band of the
Insert a bypass capacitor of 0.1 F between V
When the multiplexer circuit is used in the vertical stripe mode, C
Turn ON power to V
destruction due to latchup, and turn off power in the reverse sequence. Observe this power
sequence even during the transition period.
video signals is designed to be 9 MHz
not performed correctly.
power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage
fluctuates.
Display may not be correctly performed if noise is superimposed on the start pulse pin.
Therefore, be sure to input a reset signal during the vertical blanking period.
Even if the start pulse width is extended by half a clock or more, sampling start timing SHP
not affected, and the sampling operation is performed normally.
simultaneously sampled at the rising edge of SHP
Therefore, input a shift clock to CLI
When using the multiplexer circuit in the delta array mode or mosaic array mode, C
are sequentially sampled. Input a three-phase clock to CLI
timing, refer to 2. FUNCTION DESCRIPTION.)
The recommended timing of t
chart shows simultaneous sampling.)
pulse is input after reset, sampling is not performed in the correct sequence.
An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH
SHP
SHP
SHP
RESET
CLI
INH
1 to 3
4 to 6
7 to 9
1
PW
t
RES
ISETUP
t
R–I
DD1
, logic input, V
1
PW
R-1
2
INH
and PW
: 5 clocks
t
3
IHOLD
1
MAX
only. At this time, keep the CLI
4
DD2
RES
MIN.
. If video signals faster than that are input, display is
, and video signal input in that order to prevent
5
on starting is shown below. (The following timing
DD1
and V
n
3 clocks
. Internally, however, only CLI
1
SS1
2
MIN.
and between V
1
through CLI
3
2
and CLI
3
. (For the sampling
DD2
1
, C
and V
2
, and C
3
1
pins to "L".
, C
SS2
PD16448A
1
2
is valid.
, and C
. If the
3
1
are
is
3