UPD16488AP NEC [NEC], UPD16488AP Datasheet
UPD16488AP
Related parts for UPD16488AP
UPD16488AP Summary of contents
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DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM DESCRIPTION The µ PD16488A is a controller/driver which includes display RAM for full-dot LCDs that can provide a four-level gray scale display. This IC is able to drive full-dot LCDs ...
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BLOCK DIAGRAM....................................................................................................................................... 5 2. PIN CONFIGURATION (PAD LAYOUT) ..................................................................................................... 6 3. PIN FUNCTIONS.......................................................................................................................................... 9 3.1 Power Supply System Pins ................................................................................................................................ 9 3.2 Logic System Pins ............................................................................................................................................ 10 3.3 Driver-Related Pins........................................................................................................................................... 13 3.4 Test Pins........................................................................................................................................................... 13 4. PIN I/O CIRCUITS ...
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Line shift driver ....................................................................................................................................... 45 5.7.4 Display size settings ............................................................................................................................... 47 5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position........................................ 47 5.8 Display Modes .................................................................................................................................................. 49 5.8.1 Partial display mode ............................................................................................................................... 49 5.8.2 Monochrome (black/white) ...
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LIST OF µ µ µ µ PD16488A REGISTERS ........................................................................................................... 71 8. POWER SUPPLY SEQUENCE ................................................................................................................. 72 8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON ¡ ¡ ¡ ¡ Display ON) .................. 72 8.2 Power OFF ...
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BLOCK DIAGRAM SEG 1 Data register /RES /CS1 CS2 C86 PSX /RD(E) /WR(R,/W) D (SI (SCL) I buffer RS M SYNC DOF SIGIN1 SIGIN2 TSTIFS TSTRTST Command decoder TSTVIHL ...
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PIN CONFIGURATION (PAD LAYOUT) 2 Chip size : 3 485 µ m TYP. Chip 403 372 163 A1 164 6 : Pad size (AI µ m Pad ...
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PD16488A Pad Layout (1/2) Pad Pin Name Pad Pad Coordinate X [ µ µ m] No. Type 1 DUMMY B -1383.50 5284.00 2 DUMMY B ...
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PD16488A Pad Layout (2/2) Pad Pin Name Pad Pad Coordinate No. Type X [ µ µ m] 211 COM85 A 1274.76 -4380.00 212 COM86 A ...
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PIN FUNCTIONS 3.1 Power Supply System Pins Symbol Name Pad No. V Logic power supply 70-72, 78, 86, 94, DD1 pin 104, 146 V Boost circuit DD2 power supply pin V Logic and driver 6, 25, 28 ...
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Logic System Pins Symbol Name Pad No. PSX Data transfer selection /CS1, Chip select 90, 91, CS2 /RD Read 102, 103 (E) (enable) /WR Write 100, 101 (R,/W) (read/write) C86 Interface selection Data bus 105 to ...
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Symbol Name Pad No. CLS Select clock 76, 77 division FR Frame signal 127, 128 FR Frame 125, 126 SYNC synchronization signal DOF Display blink 130, 131 M/S Master/slave 79, 80 IRS V regulation 87, 88 LCD SIGIN1, Signature setting ...
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Symbol Name Pad No. OSC Oscillation signal 132, 133 IN1 pins OSC IN2 134, 135 OSC 136, 137 OUT OSC Display clock SYNC 139, 140 output 12 I/O Description Input A resistor can be inserted between OSC OSC -OSC . ...
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Driver-Related Pins Symbol Name Pad No. SEG to Segment 347-220 1 SEG 128 COM to Common 166 to 192, 200 to 218, 1 COM 350 to 368, 375 to 401 amp input pin RS for regulating ...
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PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The I/O circuit type of each pin and recommended connection of unused pins are described below. Pin Name Input Type PSX Schmitt trigger /CS1 Filter CS2 Filter /RD(E) Filter /WR(R,/W) ...
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DESCRIPTION OF FUNCTIONS 5.1 CPU Interface 5.1.1 Selection of interface type The PD16488A chip transfers data using an 8-bit bidirectional data bus (D polarity of the PSX pin as either H (high (low) selects between 8-bit parallel ...
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Serial interface When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read ...
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Write <CPU> /WR DATA N <Internal timing> Latch BUS N holder Write signal Read (display memory access register (R11)) <CPU> /WR /RD N DATA <Internal timing> Address preset Read signal Column address BUS holder Address set #n Figure 5-2. Write ...
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Read (other than display memory access register) <CPU> /WR /RD IRn DATA IR address set #n 18 Figure 5-2. Write and Read (2/2) IRn data IRn+1 IRn register IR address data read set # Data Sheet S15745EJ2V0DS PD16488A ...
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Display Data RAM 5.2.1 Display data RAM This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits ( bits) x 128 bits. Any specified bit can be accessed ...
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Figure 5-4. Configuration of X Address Register 00H 01H Data ...
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Column address circuit When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in Figure 5- shown in Table 5-1, the correspondence between the display RAM's column address ...
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Blink/Reverse Display Circuit The µ PD16488A enables blinking display and reverse display in designated parts of the full dot display. A blinking display is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at ...
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Figure 5-6. Setting Image of Blink/Reverse Display Area n n+1 Blink/revese data Start line End line Blinking or reverse display pixels. Example of sequence ...
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Oscillator The PD16488A include a CR-type oscillator (R external) for normal and partial display, which generates the display clocks. The clocks from this oscillator are controlled via the CLS pin and the DTY flag in the control register 2 ...
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Table 5-4. Setting of Division Level for Partial Display and Static Icon Display In four-level gray scale display mode (GRAY = L, control register 2 (R1)) Division Normal Partial Display Source Display Display Mode OSC IN1 Duty Ratio Duty Ratio ...
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Table 5-5 shows the relationship between the CLS pin, resistors RN and RP, and the display clock circuit. Table 5-5. Relationship between CLS Pin/Resistors and Display Clock Circuit RN RP CLS Connection Connection Connected Connected L Connected Not connected H ...
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Figure 5-9. Master/Slave Connection Examples (A) Master (M OSC SYNC Open (B) Master (M OSC SYNC Open Data Sheet S15745EJ2V0DS µ µ µ µ PD16488A Slave (M CLS = L) OSC ...
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Display Timing Generator The display clock generates timing signals for the line address circuit and the display data latch circuit. Display data is latched into the display data latch circuit in synch with the display clock and is output ...
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Figure 5-10. Driver Waveform Based on Frame AC Drive Method OSC SYNC FR SYNC FR RAM DATA V LCD V LC1 V LC2 SEG 1 V LC3 V LC4 ...
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Power Supply Circuit The power supply circuit supplies the voltage needed to drive the LCD. It includes a booster, voltage regulator, and voltage follower. In the power supply circuit, the power system control register 1 (R32) is used to ...
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Figure 5-11. Connection Method for Boost Levels and Capacitors Table 5-9. Boost Level Settings for Normal Display's Booster FBS2 FBS1 FBS0 ...
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Voltage regulator The boost voltage from V is supplied to the voltage regulator and output as the LCD drive voltage V OUT Since the PD16488A has a 256-step electronic volume function and an on-chip resistor for V small number ...
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Table 5-12. Values Based on Settings in Electronic Volume Register EV7 EV6 EV5 PEV7 PEV6 PEV5 Rb/ on-chip resistance factor used for the V ...
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When using an external resistor (instead of using the on-chip resistor for V Instead of using only the on-chip resistor setting for V added between V and V , between AMP such cases, the ...
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Use of op amp for level power supply control Although the PD16488A includes a circuit designed for low power consumption (HPM1, HPM0 = 0, 0), display quality problems may occur when a large-load LCD panel is used. In such ...
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Application examples of power supply circuits Figures 5-14 to 5-19 show application examples of power supply circuits. Figure 5-14. IRS = H, [OP2, OP1, OP0 Figure 5-15. IRS = L, [OP2, OP1, OP0] = [1, ...
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Figure 5-16. IRS = H, [OP2, OP1, OP0 DD1 V DD2 OUT AMP OUTP + C1 AMP OUT - LCD - LC1 ...
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Figure 5-18. IRS = L, [OP2, OP1, OP0 Open Figure 5-19. Master/Slave Connection Example V DD1 V DD2 V OUT Master Open + C5 ...
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LCD Display Drivers PD16488A includes a full dot driver. The full dot driver has a 33-level gray-scale palette (eight levels of pulse width modulation plus four-frame rate control), from which four levels of gray scale can be selected and ...
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The output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines, as shown in Figure 5-21. The pulse rising edge and falling edge combinations for each frame are listed in Table 5-15. Figure 5-21. Example of Pulse ...
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Table 5-15. Example of Pulse Width Modulated Output (1/3) Gray-scale COM 1, 2 Frames level SEG Odd SEG Even Numbered Numbered 4n+2 0 ...
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Table 5-15. Example of Pulse Width Modulated Output (2/3) Gray-scale COM 1, 2 Frames level SEG Odd SEG Even Numbered Numbered 4n+2 3 ...
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Table 5-15. Example of Pulse Width Modulated Output (3/3) Gray-scale COM 1, 2 Frames level SEG Odd SEG Even Numbered Numbered 4n+2 6 ...
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Full-dot frame rate control When combined with pulse width modulation as described in Table 5-15, the PD16488A's frame speed is based on 8- frame cycles. The subsampling pattern is output based on the palette stored in the IC. Full-Dot ...
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Line shift driver If the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the LCD's full screen, problems such as flickering may occur on the LCD panel. The PD16488A provides ...
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Figure 5-23. Line Shift Driver Image SEG SEG 1 3 SEG SEG 2 4 COM 1 COM 2 COM 3 COM 4 COM 5 COM 90 COM 91 COM 92 SEG SEG 1 3 SEG SEG 2 4 COM 1 ...
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Display size settings The PD16488A can be set for any duty value from 1/1 to 1/92. This duty setting can be made via bits DT6 to DT0 in the duty setting register (R5), as shown in Table 5-17. DT6 ...
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Table 5-19. Settings of AC Driver Inversion Position Shift Register MSD6 MSD5 MSD4 Caution The inversion ...
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Display Modes 5.8.1 Partial display mode The PD16488A includes a function for outputting a display that uses only part of the LCD panel. The duty setting for partial display mode can be selected as 1/12, 1/25, or 1/38. Parts ...
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Normal display partial display switch sequence DISP = 0 HPM1 = 1, HPM0 = 0 Switch display mode Wait time HPM1 = X, HPM0 = X DISP = 1 Note This 700 ms wait time indicates the time for ...
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Monochrome (black/white) display The PD16488A provides both a four-level gray scale display mode and a monochrome display mode. To switch to the monochrome display mode, set GRAY = H. The display RAM for one screen of monochrome display mode ...
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Figure 5-27. Relation Between the Display Data and X/Y Address 00H 01H Data ...
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Reset In the PD16488A, a reset is executed when the /RES input is at low level or when a reset command is entered. The IC is reset to its default settings. These default settings are listed in the table ...
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COMMAND REGISTERS The µ PD16488A uses a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals. Command interpretation and execution is performed using internal timing that does not depend on any external clock. Therefore, ...
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Control Register 1 (R0) This command specifies the µ PD16488A's general operation modes. E R,/W RS /RD / RMW DISP Flag RMW 0: Address is incremented after both write access and read access. 1: ...
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Control Register 2 (R1) This command specifies the µ PD16488A's general operation modes. E R,/W RS /RD / FDM Flag FDM Settings for full screen display mode 0: Normal operation 1: Full screen display ...
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Reset Command (R2) When this command is input, the IC's registers (R0 to R44) are reset to their initial values. However, the contents of memory are retained. Always input the reset command as the first command after power application. ...
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Duty Setting Register (R5) The display duty can be set to any duty ratio between 1/1 and 1/92 shown in Table 6-4. Before modifying this register, be sure to use the HALT command (control register 1 (R0)) ...
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AC Driver Inversion Cycle Register (R6) The AC driver's line position for normal display mode can be set as shown in Table 6-5. When a DTYn value is changed in the duty setting register (R5), the NIDn value is ...
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Partial AC Driver Inversion Cycle Register (R8) The AC driver's line position can be set as shown in Table 6-7. When a PDTn value is changed in the partial display mode setting register (R10), the PIDn value is automatically ...
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Partial Display Mode Setting Register (R10) This command specifies the operation mode to be used in the µ PD16488A's partial display mode. Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop ...
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Display Start Line Setting Register (R12) Display start line set specifies the top line in the display − 1 DSL6 DSL5 DSL4 Default settings (initial values set by reset command ...
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Blink Data Memory Access Register (R16) The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data is written directly to the blink data RAM. When using reset command to ...
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Inversion End Line Address Register (R19) The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when using reverse (inverted) display mode. The range of inverted lines is determined based ...
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Gray Scale Data Registers (R23 to R26) The gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. Use of this register optimizes the gray scale display. Rx Data ...
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Power System Control Register 1 (R32) This command sets the µ PD16488A's power system mode. E R,/W RS /RD / HPM1 HPM0 Flag HPM1, HPM0 These flags set the driver mode as shown in ...
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Power System Control Register 2 (R33) This command is used to control the on-chip register for V E R,/W RS /RD / − VRR2 Flag VRR2 to VRR0 When using normal display mode, power ...
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Power System Control Register 3 (R34) This command sets the power system mode, including the bias setting for the µ PD16488A's normal display mode and the number of boost levels for partial display mode ...
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Electronic Volume Register (R35) The electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display mode. Any value among 256 steps can be selected EV7 ...
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RAM Test Mode Setting Register (R44) The RAM test mode setting register directly writes the data for each type of display mode to the display RAM, as shown in Table 6-15 ...
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LIST OF µ µ µ µ PD16488A REGISTERS Index Register Index Register Control register ...
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POWER SUPPLY SEQUENCE The µ PD16488A includes power supply circuitry, such as a booster and a voltage follower. When a reset is performed using the /RES pin, the reset function is restricted prevent operation faults that ...
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Power OFF Sequence (When Using On-Chip Power Supply) Operation mode ↓ DISP = 0, HALT = 0 ↓ HPM1 = 1, HPM0 = 0 ↓ Set electronic volume register ↓ Set partial electronic volume register ↓ Power supply OFF ...
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Power Supply OFF Sequence (When Using External Driver Power Supply) Operation mode ↓ DISP = 0, HALT = 0 ↓ External driver power supply OFF ↓ DISP = 0, HALT = 1 ↓ Logic power supply OFF 74 R0 ...
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Voltage Sequence (Power ON → → → → Power OFF) OUT LCD /RES pin = 0 Power ON /RES pin = 1 DISP = 0, HALT = 1 Default settings HPM = 3 ...
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USE OF RAM TEST MODE The µ PD16488A has a test mode for writing nine types of screen data to display RAM. When using the test mode, be sure to execute via the sequence shown below. If executing the ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = +25° Parameter Logic system supply voltage Booster supply voltage Driver supply voltage Driver reference supply input voltage Logic system input voltage Logic system output voltage Logic system input/output voltage Driver ...
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Electrical Characteristics 1 (Unless Otherwise Specified −40 to +85° ° ° ° Parameter Symbol High-level input voltage V IH Low-level input voltage V IL High-level input current I IH1 Low-level input current I IL1 High-level ...
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Electrical Characteristics 2 (Unless Otherwise Specified −40 to +85° ° ° ° Parameter Symbol Current consumption I Frame frequency = 70 Hz, DD11 (normal mode) B/W all display OFF data output, 1/92 duty ...
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Required Timing Conditions (Unless Otherwise Specified, T (1) i80 CPU interface RS t AS8 /CS1 (CS2 = H) /WR, / (Write (Read) When 2.0 V ...
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When V = 2.0 to 2.5 V DD1 Parameter Symbol Address hold time t AH8 Address setup time t AS8 System cycle time t CYC8 Control low-level pulse width (/WR) t CCLW Control low-level pulse width (/RD) t CCLR Control ...
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M68 CPU interface RS R,/W t AS6 /CS1 (CS2 = (Write (Read) When V = 1.7 to 2.0 V DD1 Parameter Symbol Address hold time t AH6 ...
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When V = 2.0 to 2.5 V DD1 Parameter Symbol Address hold time t AH6 Address setup time t AS6 System cycle time t CYC6 Data setup time t DS6 Data hold time t DH6 Access time t ACC6 Output ...
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Serial interface /CS1 (CS2 = H) RS SCL SI When V = 1.7 to 2.5 V DD1 Parameter Symbol Serial clock cycle t SCYC SCL high-level pulse width t SHW SCL low-level pulse width t SLW Address hold time ...
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Common Parameter Symbol Clock input 1 f When using OSC N on-chip divider, 1/92 duty, B/W mode When using OSC on-chip divider, 1/92 duty, four-level gray scale mode Clock input 2 f When using OSC P partial display mode, ...
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Reset timing /RES Internal status When V = 1.7 to 2.5 V DD1 Parameter Symbol Reset time t R Reset low pulse width t RW Note TYP. values are reference values when T When V = 2.5 to 3.6 ...
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CPU INTERFACE (REFERENCE EXAMPLE) The µ PD16488A can be connected to either an i80 series CPU or an M68 series CPU. Also serial interface connection is used, the number of signal lines can be reduced. If several ...
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When using serial interface CPU Port1 /Port2 /RES GND 88 V DD1 RS C86 /CS1 Decoder Open SI SCL PSX /RES V SS /RESET ...
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Data Sheet S15745EJ2V0DS µ µ µ µ PD16488A 89 ...
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Data Sheet S15745EJ2V0DS µ µ µ µ PD16488A ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...