DS2482-101_12 MAXIM [Maxim Integrated Products], DS2482-101_12 Datasheet
DS2482-101_12
Related parts for DS2482-101_12
DS2482-101_12 Summary of contents
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... C masters to perform bidirectional pro- 2 tocol conversion between the I downstream 1-Wire slave devices. Relative to any attached 1-Wire slave device, the DS2482-101 is a 1-Wire master. Internal, factory-trimmed timers relieve the system host processor from generating time-critical 1-Wire waveforms, supporting both standard and over- drive 1-Wire communication speeds ...
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Single-Channel 1-Wire Master with Sleep Mode ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground.........-0.5V to +6V Maximum Current into Any Pin..........................................±20mA Operating Temperature Range ...........................-40°C to +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause ...
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Single-Channel 1-Wire Master with Sleep Mode ELECTRICAL CHARACTERISTICS (continued 2.9V to 5.5V -40°C to +85°C PARAMETER SYMBOL Write-Zero Low Time Write-Zero Recovery Time t Reset Low Time Presence-Detect Sample Time Sampling for Short and ...
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... Note 11: Applies to SDA, SCL, and AD0. Note 12: The input/output pins of the DS2482-101 do not obstruct the SDA and SCL lines if V Note 13: The DS2482-101 provides a hold time of at least 300ns for the SDA signal (referred to the V bridge the undefined region of the falling edge of SCL. ...
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... AD0 SLPZ Figure 1. Block Diagram Detailed Description The DS2482-101 is a self-timed 1-Wire master that sup- ports advanced 1-Wire waveform features including standard and overdrive speeds, active pullup, and strong pullup for power delivery. The active pullup affects rising edges on the 1-Wire side. The strong pullup function uses the same pullup transistor as the active pullup, but with a different control algorithm ...
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... The position of the read pointer, i.e., the register that the host reads in a subsequent read access, is defined by the instruc- tion the DS2482-101 executed last. To enable certain 1-Wire features, the host has read and write access to the Configuration Register. ...
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... Electrical Characteristics to determine if the internal strong pullup is sufficient given the current load on the device. If SPU is 1, the DS2482-101 treats the rising edge of the time slot in which the strong pullup starts as if the active pullup was activated. However, in contrast to the active pullup, the strong pullup, i.e., the internal pullup transis- ...
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... DS2482-101 in read mode (during the acknowledge cycle), provided that the read pointer is positioned at the Status Register. If the RST bit is 1, the DS2482-101 has performed an internal reset cycle, either caused by a power-on reset 1-Wire Busy (1WB) or from executing the Device Reset command. The RST ...
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... Single-Channel 1-Wire Master with Sleep Mode Function Commands The DS2482-101 understands eight function com- mands that fall into four categories: device control, I communication, 1-Wire setup, and 1-Wire communica- tion. The feedback path to the host is controlled by a read pointer, which is set automatically by each func- tion command for the host to efficiently access relevant information ...
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... Status Register, bits PPD and SD. Typical Use To initiate or end any 1-Wire communication sequence. 1-Wire activity must have ended before the DS2482-101 can process this command. Strong pullup (see SPU bit) should not be used in conjunction with the 1-Wire Reset command. If SPU is Restriction enabled, the PPD bit may not be valid and may cause a violation of the device’ ...
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... To perform single-bit writes or reads at the 1-Wire line when single bit communication is Typical Use necessary (the exception). Restriction 1-Wire activity must have ended before the DS2482-101 can process this command. Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is Error Response received and the command is ignored. ...
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... F1 PULLUP (SEE FIGURE 2) NOTE: DEPENDING ON ITS INTERNAL STATE, A 1-Wire SLAVE DEVICE TRANSMITS DATA TO ITS MASTER (e.g., THE DS2482-101). WHEN RESPONDING WITH 1-Wire SLAVE STARTS PULLING THE LINE LOW DURING t STARTS RISING AGAIN. WHEN RESPONDING WITH 1-Wire SLAVE DOES NOT HOLD THE LINE LOW AT ALL, AND THE VOLTAGE STARTS RISING AS SOON OVER ...
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... Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status Register (for busy polling). Note: To read the data byte received from the 1-Wire line, issue the Set Read Pointer command and select the Read Data Register. Then access the DS2482-101 Read Pointer Position in read mode ...
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... The direction byte determines the type of write time slot if both read time slots are 0 (a typical case). In this case, the DS2482-101 generates a write-one time slot and a write-zero time slot Description See Table 3 ...
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... Interface transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave. The slave address to which the DS2482-101 responds is shown in Figure 8. The logic state at the address pin AD0 determines the value of the address bit A0. The address pin allows the device to respond to one of two possible slave addresses ...
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Single-Channel 1-Wire Master with Sleep Mode SDA t BUF t LOW SCL t t HD:STA R STOP START NOTE: TIMING IS REFERENCED TO V AND V . IL(MAX) IH(MIN) 2 Figure Timing Diagram The following terminology is ...
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... Reading from the DS2482-101 To read from the DS2482-101, the master must access the device in read mode, i.e., the slave address must be sent with the direction bit set to 1. The read pointer determines the register that the master reads from. The ...
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... In the first cycle, the master sends the command. Then the master waits (Idle) for the 1-Wire reset to complete. In the second cycle, the DS2482-101 is accessed to read the result of the 1-Wire reset from the Status Register. Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed, then Read the Result ...
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... When 1WB has changed from the 1-Wire Write Byte command is completed. Case C: 1-Wire Busy (1WB = 1) S AD,0 A 1WWB A\ The master should stop and restart as soon as the DS2482-101 does not acknowledge the command code. ______________________________________________________________________________________ Communication Examples (continued) <byte> (Idle) ...
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... Register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line. Case D: 1-Wire Busy (1WB = 1) S AD,0 A 1WRB A\ The master should stop and restart as soon as the DS2482-101 does not acknowledge the command code. 1-Wire Triplet (To Perform a Search ROM Function on the 1-Wire Line) Case A: 1-Wire Idle (1WB = 0), No Busy Polling S AD,0 A 1WT A The idle time is needed for the 1-Wire function to complete ...
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... When 1WB has changed from the Status Register holds the valid result of the 1-Wire Triplet command. Case C: 1-Wire Busy (1WB = 1) S AD,0 A 1WT A\ The master should stop and restart as soon as the DS2482-101 does not acknowledge the command code PORT) μ ...
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... SDA and SCL Pullup Resistors SDA is an open-drain output on the DS2482-101 that requires a pullup resistor to realize high-logic levels. Because the DS2482-101 uses SCL only as input (no clock stretching), the master can drive SCL either through an open-drain/-collector output with a pullup resistor or a push-pull output. ...
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... RoHS status. PACKAGE TYPE 9 WLP ______________________________________________________________________________________ SLPZ AD0 B SDA GND IO WLP PACKAGE CODE OUTLINE NO. W92A1+1 21-0067 Pin Configuration TOP MARK DS2482-101 WLP Package Information LAND PATTERN NO. Refer to Application Note 1891 23 ...
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Single-Channel 1-Wire Master with Sleep Mode REVISION REVISION NUMBER DATE 0 7/08 Initial release Removed the 1-Wire line termination resistor and references to it from the Typical 1 8/08 Operating Circuit and Figure 11 Corrected the recommendation for using active ...