UPD70F3102-33 NEC [NEC], UPD70F3102-33 Datasheet
UPD70F3102-33
Related parts for UPD70F3102-33
UPD70F3102-33 Summary of contents
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PRELIMINARY DATA SHEET 32-/16-BIT SINGLE-CHIP MICROCONTROLLER The PD70F3102- product that substitutes the internal mask ROM of the memory. This enables users to perform on-board program writing and erasure, enabling effective evaluation during system development, small-lot production of multiple ...
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PIN CONFIGURATION (Top View) 144-pin plastic LQFP (fine pitch) (20 PD70F3102GJ-33-8EU PD70F3102GJ-33-UEN INTP103/DMARQ3/P07 1 INTP102/DMARQ2/P06 2 INTP101/DMARQ1/P05 3 INTP100/DMARQ0/P04 4 TI10/P03 5 TCLR10/P02 6 TO101/P01 7 TO100/P00 INTP113/DMAAK3/P17 10 INTP112/DMAAK2/P16 11 INTP111/DMAAK1/P15 12 INTP110/DMAAK0/P14 13 TI11/P13 ...
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PIN IDENTIFICATION A0 to A23: Address Bus ADTRG: AD Trigger Input ANI0 to ANI7: Analog Input AV Analog Power Supply DD Analog Reference Voltage REF AV : Analog Ground SS BCYST: Bus Cycle Start Timing CKSEL: Clock Generator ...
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INTERNAL BLOCK DIAGRAM NMI INTP100 to INTP103, INTC INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153 TO100, TO101, TO110, TO111, TO120, TO121, TO130, TO131, RPU TO140, TO141, TO150, TO151 TCLR10 to TCLR15 TI10 ...
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DIFFERENCES AMONG PRODUCTS .............................................................................................. 1.1 Differences Between PD70F3102-33 and PD703102-33 ...................................................... 1.2 Differences Between PD70F3102-33 and PD70F3102A-33.................................................. 2. PIN FUNCTIONS................................................................................................................................. 2.1 Port Pins ...................................................................................................................................... 2.2 Non-Port Pins .............................................................................................................................. 10 2.3 Pin I/O Circuit Types and Recommended Connection of Unused ...
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DIFFERENCES AMONG PRODUCTS 1.1 Differences Between PD70F3102-33 and PD703102-33 Product Item Internal ROM Flash memory Flash memory programming pin Provided (V Flash memory programming mode Provided (MODE0 = L, MODE1 = H, MODE2 = L, MODE3/V Electrical specifications Consumption ...
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PIN FUNCTIONS 2.1 Port Pins Pin Name I/O P00 I/O Port 0 8-bit I/O port P01 Input/output can be specified in 1-bit units. P02 P03 P04 P05 P06 P07 P10 I/O Port 1 8-bit I/O port P11 Input/output can ...
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Pin Name I/O P50 to P57 I/O Port 5 8-bit I/O port Input/output can be specified in 1-bit units. P60 to P67 I/O Port 6 8-bit I/O port Input/output can be specified in 1-bit units. P70 to P77 Input Port ...
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Pin Name I/O P110 I/O Port 11 8-bit I/O port P111 Input/output can be specified in 1-bit units. P112 P113 P114 P115 P116 P117 P120 I/O Port 12 8-bit I/O port P121 Input/output can be specified in 1-bit units. P122 ...
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Non-Port Pins Pin Name I/O TO100 Output Pulse signal output of timers TO101 TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TO150 TO151 TCLR10 Input External clear signal input of timers TCLR11 TCLR12 ...
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Pin Name I/O INTP130 Input External maskable interrupt request input, or timer 13 external capture trigger input INTP131 INTP132 INTP133 INTP140 Input External maskable interrupt request input, or timer 14 external capture trigger input INTP141 INTP142 INTP143 INTP150 Input External ...
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Pin Name I/O LCAS Output Column address strobe signal output for lower data of DRAM UCAS Output Column address strobe signal output for higher data of DRAM RAS0 to RAS3 Output Row address strobe signal output for DRAM RAS4 RAS5 ...
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Pin Name I/O AV – Ground potential for A/D converter SS CV – Positive power supply for the dedicated clock generator DD CV – Ground potential for dedicated clock generator SS V – Positive power supply (internal unit power supply) ...
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Pin I/O Circuit Types and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins, and Figure 2-1 shows the schematic circuit diagram for each I/O circuit ...
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Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2) I/O Circuit Pin Type P80/CS0/RAS0 to P83/CS3/RAS3 5 P84/CS4/RAS4/IOWR, P85/CS5/RAS5/IORD P86/CS6/RAS6, P87/CS7/RAS7 P90/LCAS/LWR P91/UCAS/UWR P92/RD P93/WE P94/BCYST P95/OE P96/HLDAK P97/HLDRQ P100/TO120, P101/TO121 5 P102/TCLR12, P103/TI12 5-K P104/INTP120/TC0 ...
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Figure 2-1. Pin Input/Output Circuits Type P-ch IN N-ch Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Input enable Caution Replace V in the circuit diagrams with HV ...
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FLASH MEMORY PROGRAMMING The following two flash memory programming methods are available. (1) On-board programming The program is written to the flash memory using a dedicated flash programmer after the PD70F3102-33 is mounted on the target board. Install the ...
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Flash Memory Programming Functions Flash memory programming is performed by sending and receiving commands and data according to the selected communication mode. Table 3-2 shows the main flash memory programming functions. Table 3-2. Main Flash Memory Programming Functions Function ...
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ELECTRICAL SPECIFICATIONS 4.1 Normal Operation Mode Absolute Maximum Ratings (T = 25°C) A Parameter Symbol Supply voltage Input voltage V I Clock input voltage V K Output ...
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Capacitance (T = 25° Parameter Symbol Input capacitance C I I/O capacitance C IO Output capacitance C O Operating Conditions Operation Internal Operation Clock Frequency Mode ( ) Direct mode 10 to ...
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Recommended Oscillator (a) Connection of ceramic resonator (T (i) Murata Mfg. Co., Ltd –40 to +85°C) A Type Product Name Oscillation Frequency f XX Surface CSAC4.00MGC040 mount CSTCC4.00MG0H6 CSAC5.00MGC040 CSTCC5.00MG0H6 CSAC6.60MT CSTCC6.60MG0H6 CSAC8.00MT CSTCC8.00MG0H6 Lead CSA4.00MG040 CST4.00MGW040 CSA5.00MG040 ...
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TDK Corporation (T = –40 to +85°C) A Manufacturer Product Name Oscillation Frequency f XX TDK CCR4.0MC3 CCR5.0MC3 CCR8.0MC5 Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible not wire any ...
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External clock input (T = –40 to +85°C) A Caution Input a CMOS level voltage to the X1 pin. Cautions when turning on/off the power The PD70F3102-33 is configured with power supply pins for the internal unit (V (HV ...
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DC Characteristics (T = –40 to 85° Parameter Symbol Input voltage, high V IH Input voltage, low V IL Clock input voltage, high V XH Clock input voltage, low Schmitt-triggered input HV T threshold voltage ...
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DC Characteristics (T = –40 to 85° Parameter Symbol Supply During normal I DD1 current During HALT I DD2 During IDLE I DD3 During STOP I DD4 Remarks 1. TYP. values are reference values for when T 2. ...
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Data Retention Characteristics (T = –40 to +85°C) A Parameter Symbol Data retention voltage V DDDR HV DDDR Data retention current I DDDR Supply voltage rise time t RVD Supply voltage fall time t FVD Supply voltage hold time t ...
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AC Characteristics (T = –40 to +85° Load Capacitance pF Test Input Waveforms (a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P107/INTP123/TC3, P114/INTP140, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, ...
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Clock timing Parameter X1 input cycle <1> X1 input high-level width <2> X1 input low-level width <3> X1 input rise time <4> X1 input fall time <5> CPU operating frequency – CLKOUT output cycle <6> CLKOUT high-level width <7> ...
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Output waveform (other than X1, CLKOUT) Parameter Output rise time <12> Output fall time <13> Signals other than X1, CLKOUT (3) Reset timing Parameter RESET pin high-level width <14> RESET pin low-level width <15> Remark T : Oscillation stabilization ...
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SRAM, external ROM, external I/O access timing (a) Access timing (SRAM, external ROM, external I/O) (1/2) Parameter Address, CSn output delay time <16> (from CLKOUT ) Address, CSn output hold time <17> (from CLKOUT ) RD, IORD delay time ...
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Access timing (SRAM, external ROM, external I/O) (2/2) CLKOUT (Output A23 (Output) CSn (Output) BCYST (Output) RD, IORD (Output) [Read time] UWR, LWR, IOWR (Output) [Write time (I/O) [Read time (I/O) ...
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Read timing (SRAM, external ROM, external I/O) (1/2) Parameter Data input setup time (to address) <30> Data input setup time (to RD) <31> RD, IORD low-level width <32> RD, IORD high-level width <33> Delay time from address, CSn to ...
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Read timing (SRAM, external ROM, external I/O) (2/2) CLKOUT (Output A23 (Output) CSn (Output) UWR, LWR, IOWR (Output) RD, IORD (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. Timing when the number of waits ...
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Write timing (SRAM, external ROM, external I/O) (1/2) Parameter WAIT setup time (to address) <38> WAIT setup time (to BCYST ) <39> WAIT hold time (from BCYST ) <40> Delay time from address, CSn to <41> UWR, LWR, IOWR ...
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Write timing (SRAM, external ROM, external I/O) (2/2) CLKOUT (Output A23 (Output) CSn (Output) RD, IORD (Output) UWR, LWR, IOWR (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. Timing when the number of waits ...
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DMA flyby transfer timing (SRAM Parameter WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> RD low-level width <32> RD high-level width <33> Delay time from address, CSn to <34> RD Delay time from ...
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DMA flyby transfer timing (SRAM CLKOUT (Output A23 (Output) CSn (Output) RD (Output) UWR, LWR (Output) DMAAKm (Output) IORD (Output) IOWR (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. Timing when the number of ...
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DMA flyby transfer timing (external I/O Parameter WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> IORD low-level width <32> IORD high-level width <33> Delay time from address, CSn to <34> IORD Delay time ...
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DMA flyby transfer timing (external I/O CLKOUT (Output A23 (Output) CSn (Output) UWR, LWR (Output) RD (Output) DMAAKm (Output) IOWR (Output) IORD (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. Timing when the number ...
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Page ROM access timing (1/2) Parameter WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> Data input setup time <26> (to CLKOUT ) Data input hold time <27> (from CLKOUT ) Off-page data input ...
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Page ROM access timing (2/2) CLKOUT (Output) Note Off-page address CSn (Output) Note On-page address UWR, LWR (Output) RD (Output D15 (I/O) WAIT (Input) BCYST (Output) Note On-page addresses and off-page addresses are as follows. PRC Register ...
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DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3) Parameter WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> Data input setup time (to CLKOUT ) <26> Data input ...
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Read timing (high-speed page DRAM access, normal access: off-page) (2/3) Parameter Symbol RAS column address delay time <76> RAS to CAS delay time <77> Output buffer turn off delay time <78> (from OE ) Output buffer turn off delay ...
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Read timing (high-speed page DRAM access, normal access: off-page) (3/3) TRPW CLKOUT (Output) <56> A23 (Output) <61> RASn (Output) <66> UCAS (Output) LCAS (Output) WE (Output) OE (Output D15 (I/O) WAIT (Input) Remarks 1. These ...
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Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 45 ...
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Read timing (high-speed DRAM access: on-page) (1/2) Parameter Data input setup time (to CLKOUT ) <26> Data input hold time (from CLKOUT ) <27> Delay time from OE to data output <37> Column address setup time <58> Column address ...
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Read timing (high-speed DRAM access: on-page) (2/2) CLKOUT (Output A23 (Output) RASn (Output) UCAS (Output) LCAS (Output) WE (Output) OE (Output D15 (I/O) WAIT (Input) Remarks 1. These timings are for the following cases (n ...
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Write timing (high-speed page DRAM access, normal access: off-page) (1/2) Parameter WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> Row address setup time <56> Row address hold time <57> Column address setup time ...
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Write timing (high-speed page DRAM access, normal access: off-page) (2/2) TRPW CLKOUT (Output) <56> A23 (Output) <61> RASn (Output) <66> UCAS (Output) LCAS (Output) OE (Output) WE (Output D15 (I/O) WAIT (Input) Remarks 1. These ...
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Write timing (high-speed page DRAM access: on-page) (1/2) Parameter Column address setup time <58> Column address hold time <59> RAS hold time <63> Column address read time (from <64> RAS ) CAS pulse width <65> CAS precharge time <81> ...
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Write timing (high-speed page DRAM access: on-page) (2/2) CLKOUT (Output A23 (Output) RASn (Output) UCAS (Output) LCAS (Output) OE (Output) WE (Output) <90> D15 (I/O) WAIT (Input) Remarks 1. These timings are for the following ...
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Read timing (EDO DRAM) (1/3) Parameter Data input setup time (to <26> CLKOUT ) Data input hold time (from <27> CLKOUT ) Delay time from OE to data output <37> Row address setup time <56> Row address hold time ...
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Read timing (EDO DRAM) (2/3) Parameter Symbol Output enable Off-page <99> access time On-page <100> Remarks CYK Number of waits specified by RPCxx bit of register DRCn ( ...
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Read timing (EDO DRAM) (3/3) TRPW CLKOUT (Output) <56> A23 (Output) <61> RASn (Output) <66> UCAS (Output) LCAS (Output) WE (Output) OE (Output D15 (I/O) BCYST (Output) WAIT (Input) Note In case of on-page access ...
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Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 55 ...
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Write timing (EDO DRAM) (1/2) Parameter Row address setup time <56> Row address hold time <57> Column address setup time <58> Column address hold time <59> RAS precharge time <61> RAS hold time <63> Column address read time <64> ...
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Write timing (EDO DRAM) (2/2) TRPW CLKOUT (Output) <56> A23 (Output) Row address <61> RASn (Output) <66> UCAS (Output) LCAS (Output) RD (Output) OE (Output) WE (Output D15 (I/O) BCYST (Output) WAIT (Input) Remarks 1. ...
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DMA flyby transfer timing (DRAM (EDO, high-speed page) Parameter WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> Delay time from OE to data output <37> Delay time from address to IOWR <41> Address ...
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DMA flyby transfer timing (DRAM (EDO, high-speed page) Parameter Symbol Output buffer turn-off delay time <78> (from OE ) Output buffer turn-off delay time <79> (from CAS ) CAS precharge time <81> High-speed mode cycle time <82> RAS hold ...
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DMA flyby transfer timing (DRAM (EDO, high-speed page) TRPW CLKOUT (Output) <56> A23 (Output) Row address <61> RASn (Output) <66> UCAS (Output) LCAS (Output) RD (Output) OE (Output) DMAAKm (Output) WE (Output) IORD (Output) <41> IOWR (Output) ...
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DMA flyby transfer timing (external I/O Parameter Symbol WAIT setup time (to CLKOUT ) <24> WAIT hold time (from CLKOUT ) <25> IORD low-level width <32> IORD high-level width <33> Delay time from address to IORD <34> Delay time ...
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DMA flyby transfer timing (external I/O Parameter WE setup time Off-page <101> (to CAS ) On-page <102> Delay time from DMAAKm to <105> CAS Delay time from IORD to CAS <106> Delay time from WE to IORD <107> Remarks ...
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DMA flyby transfer timing (external I/O T1 TRPW CLKOUT (Output) <56> A23 (Output) Row address <61> RASn (Output) <66> UCAS (Output) LCAS (Output) <71> RD (Output) OE (Output) WE (Output) DMAAKm (Output) IOWR (Output) <34> IORD (Output) ...
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CBR refresh timing Parameter RAS precharge time <61> RAS pulse width <62> CAS hold time <108> REFRQ pulse width <109> RAS precharge CAS hold time <110> REFRQ active delay time <111> (from CLKOUT ) REFRQ inactive delay time <112> ...
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CBR self refresh timing Parameter Symbol REFRQ active delay time <111> (from CLKOUT ) REFRQ inactive delay time <112> (from CLKOUT ) CAS hold time <114> RAS precharge time <115> Remarks CYK ...
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DMAC timing Parameter DMARQn setup time <116> (to CLKOUT ) DMARQn hold time <117> (from CLKOUT ) <118> DMAAKn output delay time <119> (from CLKOUT ) DMAAKn output hold time <120> (from CLKOUT ) TCn output delay time <121> ...
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Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 67 ...
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Bus hold timing (1/2) Parameter HLDRQ setup time (to CLKOUT ) <123> HLDRQ hold time <124> (from CLKOUT ) Delay time from CLKOUT to <125> HLDAK HLDRQ high-level width <126> HLDAK low-level width <127> Delay time from CLKOUT to ...
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Bus hold timing (2/2) T1 CLKOUT (Output) <123> <124> HLDRQ (Intput) HLDAK (Output A23 (Output D15 (I/O) CSn/RASn (Output) BCYST (Output) RD (Output) WE (Output) UCAS (Output) LCAS (Output) Remarks 1. Broken lines indicate high ...
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Interrupt timing Parameter NMI high-level width <132> NMI low-level width <133> INTPn high-level width <134> INTPn low-level width <135> Remarks 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and ...
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UART0, UART1 timing (synchronized with clock, master mode only) Parameter SCKn cycle <140> SCKn high-level width <141> SCKn low-level width <142> RXDn setup time (to SCKn ) <143> RXDn hold time (from SCKn ) <144> TXDn output delay time ...
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CSI0 to CSI3 timing (a) Master mode Parameter SCKn cycle <147> SCKn high-level width <148> SCKn low-level width <149> SIn setup time (to SCKn ) <150> SIn hold time (from SCKn ) <151> SOn output delay time (from SCKn ...
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A/D Converter Characteristics (T = – – 0 Output Pin Load Capacitance Parameter Symbol Resolution – Overall error – Quantization error ...
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Flash Memory Programming Mode Basic Characteristics ( (When Rewriting Parameter Symbol Operating frequency f X Power supply voltage PPH HV supply current ...
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Serial Write Operation Characteristics Parameter set time <201> RESET set time <202> PP RESET to V count start time <203> PP Count execution time <204> V counter high-level width <205> counter ...
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PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) 108 109 144 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC LQFP (FINE PITCH) (20x20) 108 109 144 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. Preliminary Data Sheet U13844EJ2V0DS00 ...
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RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document “Semiconductor Device Mounting Technology Manual (C10535E)”. For soldering methods and conditions other ...
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Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 79 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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Related Documents PD70F3102A-33 Data Sheet (U13845E) PD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet (U13995E) PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E) Reference Materials Electrical Characteristics for Microcomputer (IEI-601) Note This document number is that of Japanese version. The related documents in ...