UPD70F3102-33 NEC [NEC], UPD70F3102-33 Datasheet - Page 38

• Manufacturer Part Number: UPD70F3102-33
• Description: 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
• Manufacturer: NEC [NEC]

38
WAIT setup time (to CLKOUT )
WAIT hold time (from CLKOUT )
IORD low-level width
IORD high-level width
Delay time from address, CSn to
IORD
Delay time from IORD to address
Delay time from IORD to data
output
WAIT setup time (to address)
WAIT setup time (to BCYST )
WAIT hold time (from BCYST )
Delay time from address to UWR,
LWR
Address setup time (to UWR,
LWR )
Delay time from UWR, LWR to
address
UWR, LWR high-level width
UWR, LWR low-level width
Delay time from UWR, LWR to
IORD
Delay time from DMAAKm to
IORD
Delay time from IORD to
DMAAKm
Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.
Remarks 1. T = t
(e) DMA flyby transfer timing (external I/O
Parameter
2. w: Number of waits due to WAIT
3. w
4. w
5. i: Number of idle states inserted when a write cycle follows the read cycle.
6. n = 0 to 7, m = 0 to 3
D
F
: Number of waits inserted to source-side access during DMA flyby transfer.
: Number of waits specified by registers DWC1 and DWC2.
CYK
<24>
<25>
<32>
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
<44>
<45>
<48>
<51>
<52>
Symbol
Preliminary Data Sheet U13844EJ2V0DS00
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DRDOD
DWRRD
WWRH
DDARD
DRDDA
t
t
WRDH
t
WWRL
WRDL
SBSW
HBSW
DAWR
SAWR
DWRA
DARD
DRDA
HKW
SWK
SAW
Note
Note
Note
w
w
Conditions
SRAM transfer) (1/2)
F
F
= 0
= 1
(1 + w
(1.5 + w
(1 + w
(0.5 + i) T – 10
(0.5 + i) T – 10
D
0.5T – 10
0.5T – 10
0.5T – 10
0.5T – 10
0.5T – 10
+ w
D
T – 10
T – 10
T – 10
MIN.
D
+ w) T – 10
15
+ w) T – 10
2
F
0
0
+ w) T – 10
T – 25
T – 25
MAX.
PD70F3102-33
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns