UPD72042BGT NEC [NEC], UPD72042BGT Datasheet
UPD72042BGT
Available stocks
Related parts for UPD72042BGT
UPD72042BGT Summary of contents
Page 1
LSI DEVICE FOR Inter Equipment Bus The PD72042B is a microcomputer peripheral LSI device for IEBus protocol control. The PD72042B performs all the processing required for layers 1 and 2 of the IEBus. The device incorporates large transmission and reception ...
Page 2
PIN CONFIGURATION (TOP VIEW) • 16-pin plastic SOP (9.53 mm (375)) PD72042BGT SCK Note SI(SIO) Note SO(NC) IRQ C/D XO GND Note Parentheses indicate the state corresponding to two-wire serial I/O mode Main power supply for IEBus (connected ...
Page 3
BLOCK DIAGRAM Data link controller Internal bus Receiver BUS + BUS – Filter Driver Contention detection section Parity generation section Parity detection section generation Test circuit TEST Remark The pin names in parentheses are used when two-wire serial I/O is ...
Page 4
PIN FUNCTIONS ............................................................................................................................. 1.1 PIN FUNCTIONS ..................................................................................................................................... 2. IEBus OPERATION ......................................................................................................................... 2.1 OVERVIEW .............................................................................................................................................. 2.2 IEBus COMMUNICATION PROTOCOL ................................................................................................ 2.2.1 Bus Mastership Determination (Arbitration) ............................................................................... 10 2.2.2 Communication Mode ................................................................................................................. 10 2.2.3 Communication Address ............................................................................................................. 2.2.4 Broadcast ..................................................................................................................................... 2.3 ...
Page 5
RECOMMENDED SOLDERING CONDITIONS ............................................................................. 87 APPENDIX A MAIN DIFFERENCES BETWEEN PD72042A, PD72042B, AND PD6708 ......... 88 APPENDIX B IEBus PROTOCOL ANALYZER .................................................................................. 88 Data Sheet S13990EJ3V0DS PD72042B 5 ...
Page 6
PIN FUNCTIONS 1.1 PIN FUNCTIONS Note Note Pin No. Pin I/O Serial clock input pin for CPU interface 1 SCK Input Serial data pin for CPU interface. (This pin 2 SI (SIO) Input (I/O) functions as an input pin ...
Page 7
Pin No. Pin I/O Serial reset signal input pin. A low input causes 14 RESET Input a reset. Whenever the power is turned on, a low-level signal must be applied to this pin. During normal operation, a high level is ...
Page 8
IEBus OPERATION 2.1 OVERVIEW The PD72042B is a CMOS LSI device for the IEBus interface. The IEBus is designed to enable the data transmission between devices in a small-scale digital data transmission system. The PD72042B is connected to a ...
Page 9
IEBus COMMUNICATION PROTOCOL The IEBus is outlined below. • Communication method: Half duplex asynchronous communication • Multi-master method All units connected to the IEBus can transmit data to every other connected unit. • Broadcast function (one-unit-to-multiple-units communication) Group broadcast ...
Page 10
Bus Mastership Determination (Arbitration) Before devices connected to the IEBus can control other devices, they must first acquire the bus. This operation is called arbitration. When more than one unit starts transmission at the same time, arbitration determines which ...
Page 11
Communication Address With the IEBus, each device is assigned a unique 12-bit communication address. The communication address consists of the following parts: High-order 4 bits : Group number (number identifying the group to which a device belongs) Low-order 8 ...
Page 12
Fig. 2-1 Transmission Signal Format Field name Header Master address field Number of bits Broad- Start Master P cast bit address address bit Transmission time Mode 0 Mode Parity bit (1 bit) A ...
Page 13
Master address field The master address field is used to transmit the local unit address (master address) to other units. The master address field consists of master address bits and a parity bit. A master address consists of 12 ...
Page 14
Control field The control field indicates the type and direction of the next data field. The control field consists of control bits, a parity bit, and an acknowledge bit. The four control bits are output starting with the MSB. ...
Page 15
Master reception The data-length bits and parity bit are output by the slave unit. When the master unit detects even parity, the master unit outputs the acknowledge signal. If the master unit detects odd parity, the master unit does ...
Page 16
Parity bit A parity bit is used to check for errors in the transmission data. A parity bit is added to the master address bits, slave address bits, control bits, data-length bits, and data bits. Even parity is used. ...
Page 17
Acknowledge bit at the end of the data-length field If any of the following is detected, the acknowledge bit at the end of the data-length field is set to NAK, and transmission is stopped: • The parity of the ...
Page 18
Table 2-3 Meanings of the Control Bits Note 1 Bit 3 Bit 2 Bit ...
Page 19
Fig. 2-2 Slave Status (SSR) Bit Format MSB bit 7 bit 6 Table 2-5 Slave Status Meanings Bit Value Note 1 Bit Note 2 Bit Bit Bit 3 0 Note 3 ...
Page 20
Reading a lock address (control bits: 4H, 5H) When a lock address read operation (4H, 5H) is specified, the address (12 bits) of the master unit that issued the lock instruction is read in one-byte form, as shown below. ...
Page 21
BIT FORMAT Fig. 2-4 illustrates the bits that constitute an IEBus communication frame. Fig. 2-4 IEBus Bit Format (Concept) Logic "1" Logic "0" Preparation Synchronization period period Logic 1: The potential difference between the bus lines (the BUS+ and ...
Page 22
MICROCOMPUTER INTERFACE 3.1 TRANSFER METHOD Either of two microcomputer interface modes can be selected: three-wire serial I/O mode or two-wire serial I/O mode. Whether three-wire serial I/O mode or two-wire serial I/O mode is selected depends on the input ...
Page 23
Table 3-1 I/O States of the SIO (SI) and SO Pins RESET CS SEL C Input state O : Output state O* : State in which 1 ...
Page 24
Data read mode When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data read mode, the data in a read register is read on the SO ...
Page 25
Two-Wire Data Transfer (SEL = 0) (1) Control mode When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the following processing. 1 Register address setting 2 Register read/write selection ...
Page 26
Data write mode C/D SCK Note SIO Control mode State (selection of register write) Serial clock counter reset pointer Note SIO pin input state Caution Register overwrite is started immediately after the eighth clock rising edge. All registers other ...
Page 27
CONNECTION TO A MICROCOMPUTER (1) Three-wire serial I/O 120 5 V 180 180 120 (2) Two-wire serial I/O 120 5 V 180 180 120 Notes 1. When only the PD72042B controlled from a microcomputer via a ...
Page 28
STANDBY MODE SETTING AND CANCELLATION Standby mode can be set by setting STREQ of the CTR register to 1. The XI pin for oscillation is tied to GND, and the impedance of the XO pin goes high. In standby ...
Page 29
REGISTERS A microcomputer controls IEBus communication by reading from and writing to the internal registers of the PD72042B. Registers are classified into write registers and read registers. The total size of the write registers is 40 bytes; the transmission ...
Page 30
Write registers Address Name High-order 4 bits 0H 0000 CTR – 1H 0001 CMR 0 LOCK 1 2H 0010 UAR1 Local station address (low-order 4 bits) 3H 0011 UAR2 4H 0100 SAR1 Slave address (low-order 4 bits) 5H 0101 ...
Page 31
Cautions 1. In standby mode (with STM of the FLG register set to 1), the user can only write to the CTR register (including standby mode cancellation) and read from the FLG register. 2. Never access a free address. 3. ...
Page 32
CMR Command register CMR is a one-byte write register used to set a command for communication control, transmission/reception buffer control, or optional function setting. When data is set in CMR from the microcomputer, CEX of the FLG register is set ...
Page 33
Notes 2. When the MSB of the control bits set in MCR is 1 (for master transmission), set the number of bytes of transmission data, and at least one byte of transmission data in TBF before command setting. 3. When ...
Page 34
UAR1 UAR2 Local station unit address register UAR1 and UAR2 are registers used to set a local station unit address (12 bits) and condition code. Set UAR1 and UAR2 after reset cancellation. b7 Local station address (low-order 4 bits) b7 ...
Page 35
SAR1 SAR2 Slave address register The SAR1 and SAR2 registers are used to set the address of a remote station (slave address) in master communication. Set SAR1 and SAR2 while the value of MARQ of the FLG register is 0 ...
Page 36
MCR Master communication register The MCR register is used to set a master communication condition. Set MCR while the value of MARQ of the FLG register is 0 (while master communication is not requested Broadcast bit Number of ...
Page 37
This control field is used to set the control bits (four bits). • Contents of control bits Note 1 Bit 3 Bit ...
Page 38
TBF Transmission buffer TBF is a 33-byte FIFO buffer used to hold the number of bytes of transmission data and transmission data for master transmission and slave data transmission. TBF can be written from the microcomputer when the TFL flag ...
Page 39
STR Status register STR is a one-byte read register used to indicate the states of TBF and RBF TFL TEP [TFL TBF is full TBF is not full. The microcomputer can load data into ...
Page 40
FLG Flag register FLG is a one-byte read register used to indicate statuses such as the communication state, command execution state, and interrupt state — MARQ [MARQ request for communication as the master unit is ...
Page 41
A command is currently being executed Execution of a command has terminated. A command code can be set in CMR. The CEX flag is set and reset as described below. • Set : When a ...
Page 42
RDR1 RDR2 Reception data register The RDR1 and RDR2 registers are used to hold the number of bytes of reception data stored in RBF for each frame received during master, slave, or broadcast reception. b7 Number of bytes of master ...
Page 43
LOR1 LOR2 Lock register The LOR1 and LOR2 registers are used to hold a lock state. LOR1 and LOR2 set a lock state and lock address after the lock state setting command is set in the CMR register (LOCK = ...
Page 44
DAR1 DAR2 Broadcast address register The DAR1 and DAR2 registers are used to hold a broadcast address (master address) involved when a broadcast reception error occurs. DAR1 and DAR2 are updated each time a broadcast reception error occurs (SLRC of ...
Page 45
RCR Return code register RCR is a one-byte read register used to indicate the IEBus communication status (return code). RCR consists of two return codes: MARC and SLRC. MARC indicates the communication status in master transmission or master reception. SLRC ...
Page 46
Table 4-2 MARC Return Codes for Master Transmission MARC 0000 1. Meaning: Master transmission is started. 2. Occurrence condition: This return code is issued when the master address field in a communication frame has been transmitted, and the unit has ...
Page 47
Table 4-3 MARC Return Codes for Master Communication MARC 0100 1. Meaning: Master reception has started. 2. Occurrence condition: 1 The unit has won the arbitration to become the master unit, and a communication frame up to the data-length field ...
Page 48
When master transmission is performed Return codes for master Return codes for master transmission transmission and master reception Ta 0000 0010 0011 0110 0111 Tb 0011 Table 4-4 Minimum Return Code Occurrence Interval for Master Transmission ...
Page 49
When master reception is performed Return codes for master Return codes for master reception transmission and master reception 0010 0100 0011 0110 0111 Tb 0111 Table 4-5 Minimum Return Code Occurrence Interval for Master Reception (t: ...
Page 50
SLRC indicates the communication status for slave data transmission, slave reception, or broadcast reception. (a) Slave data transmission Slave data transmission is performed when the microcomputer makes the setting described below. • Slave data transmission setting In COMC of ...
Page 51
Slave reception Slave reception is performed when the broadcast bit is set to 1, and a communication frame with the local station address specified in the slave address field is received. Table 4-7 indicates the SLRC return codes for ...
Page 52
Broadcast reception Broadcast reception is performed when the broadcast bit is set to 0, and a communication frame with FFH (general broadcast) or the local station group address specified in the slave address field is received. Table 4-8 indicates ...
Page 53
Table 4-9 indicates the SLRC return code issued in broadcast reception when an optional function is set in the CMR register with DERC = 1. Table 4-9 SLRC Return Code in Broadcast Reception When the Optional Function Is Set (DERC ...
Page 54
When slave data transmission is performed Return codes for broadcast reception, slave data Return codes for slave data transmission transmission, and slave reception 0010 0011 0110 Ta 0000 0111 1010 1011 1100 Table 4-10 Minimum Return ...
Page 55
When slave reception is performed Return codes for broadcast reception, slave data Return codes for slave reception transmission, and slave reception 0010 0011 0110 Tb 0111 Ta Tb 1010 0100 1011 1100 Table 4-11 Minimum Return Code Occurrence Interval ...
Page 56
When broadcast reception is performed Return codes for broadcast reception, slave data transmission, and slave reception 0010 0011 0110 0111 Ta 1010 1000 1011 1100 Tb 1100 Table 4-12 Minimum Return Code Occurrence Interval for Broadcast Reception (t: At ...
Page 57
RBF Reception buffer RBF is a 40-byte FIFO buffer used to hold a transmitter address, control bits, data-length bits, and reception data for master reception, slave reception, or broadcast reception. RBF can be read by the microcomputer when the REP ...
Page 58
Transmitter address As indicated below, the transmitter address depends on whether the communication mode is master reception, slave reception, or broadcast reception. • Transmitter address Case Transmitter address Master reception Slave address Slave ...
Page 59
EXAMPLE TIMINGS FOR COMMUNICATION This chapter provides examples of the timings at which the contents of internal registers change during communication. The following seven examples are given: (1) Master transmission timing example 1 Timing at which a return code ...
Page 60
Control field Data-length field Communication frame CMR COMC 1000 CEX MARQ FLG STRQ "0" SLRE MARC RCR SLRC (Slave reception started) IRQ pin Minimum time Approx. 2430 s (mode 0) Approx. 740 s (mode 1) (when MHz) ...
Page 61
Master Slave Communication frame address bits address bits CMR COMC "0" CEX MARQ FLG "0" STRQ SLRE "1" MARC 0000 (Master transmission started) RCR SLRC STR TEP TBF IRQ pin Data-length ...
Page 62
Control field Data-length field Communication frame CMR COMC 1011 CEX "0" MARQ FLG STRQ SLRE MARC RCR SLRC (Slave reception started) IRQ pin Minimum time Approx. 5420 s (mode 0) (when MHz) Approx. 1490 s (mode 1) ...
Page 63
Communication frame Control field Data-length field CMR COMC 1000 CEX MARQ FLG "0" STRQ SLRE MARC RCR SLRC (Slave reception started) RDR1 IRQ pin Minimum time Approx. 7150 s (mode 0) (when MHz) Approx. 1920 s (mode ...
Page 64
Communication frame Control field Data-length field Separate frame (data-length bits: N1) CTR REEN CEX "0" MARQ "0" FLG STRQ "0" SLRE MARC RCR SLRC (Broadcast reception started) RDR2 3 4 IRQ pin Approx. 5260 s (mode 0) Minimum time (when ...
Page 65
Data-length P A Communication frame Data 1 0 bits: 24 ACK CMR LOCK CEX "0" MARQ FLG "0" STRQ SLRE MARC RCR 0100 (Slave reception started) SLRC STR RFL LOR1, LOR2 RBF IRQ pin Minimum time Approx. 1570 s (mode ...
Page 66
Communication frame Control field Data-length field Separate frame "0" CTR REEN "0" CEX MARQ "0" FLG "0" STRQ SLRE MARC RCR SLRC (Slave reception started) RFL STR DAR1, DAR2 IRQ pin Minimum time Approx. 5420 s (mode 0) (when f ...
Page 67
EXAMPLE MICROCOMPUTER PROCESSING FLOW This chapter provides an example of the processing flow for controlling the PD72042B from the microcomputer. The main parts of this example processing flow are the following two routines: • Main routine Performs processing based ...
Page 68
COMMUNICATION FLAGS Table 6-1 lists the communication flags used in the main and interrupt routines, excluding those flags assigned to the registers of the PD72042B. Name RAWF Program crash detection flag (1: Detected, 0: Not detected) TRRQ Transmission processing ...
Page 69
MAIN ROUTINE Fig. 6-1 shows the processing flow of the main routine. Fig. 6-1 Processing Flow of Main Routine Start PD72042B initial setting routine Communication flag initialization routine RAWF? 0 TRRQ? 0 RERQ? 0 Note MCRQ ? 0 Note ...
Page 70
INTERRUPT ROUTINE The interrupt routine performs the required processing when an interrupt request is issued from the PD72042B. The interrupt routine disables the interrupts received from the PD72042B, reads the statuses (FLG and RCR registers) of the PD72042B, and ...
Page 71
Fig. 6-3 Flow of Interrupt Routine RAWF 1 00 TRCF MARC TRRQ 1 TRCF SLRC TRRQ 1 Notes 1. The return code in MARC is enabled when any of conditions below, is satisfied: ...
Page 72
PROCESSING ROUTINES This section describes the processing routines called from the main routine. 6.4.1 PD72042B Initial Setting Routine This routine is executed when the PD72042B is first started or upon the detection of a program crash (RAW = 1). ...
Page 73
Command Processing Routine This routine is executed when CORQ has been set by the application processing routine. The command processing routine sets a command code, in the CMR register, to set the lock state, control transmission/reception buffers, control communication, ...
Page 74
Master transmission processing routine 1 Fig. 6-6 shows the flow of master transmission processing routine 1. Fig. 6-6 Flow of Master Transmission Processing Routine 1 Start SAR1 Slave address (four low-order bits) SAR2 Slave address (eight high-order bits) MCR ...
Page 75
Master transmission processing routine 2 Fig. 6-7 shows the flow of master transmission processing routine 2. Fig. 6-7 Flow of Master Transmission Processing Routine 2 Start I > Number of bytes in tranmission data Read STR TFL? I TBF ...
Page 76
Master reception processing routine Fig. 6-8 shows the flow of the master reception processing routine. Fig. 6-8 Flow of Master Reception Processing Routine SAR1 Slave address (four low-order bits) SAR2 Slave address (eight high-order bits) MCR Broadcast bits, number ...
Page 77
Slave Data Transmission Processing Routine This routine is executed when SDRQ has been set by the application processing routine. The slave data transmission processing routine consists of the following two processing routines: • Slave data transmission processing routine 1 ...
Page 78
Fig. 6-9 Flow of Slave Data Transmission Processing Routine 1 Start Read STR TEP? 0 Read FLG 1 CEX? 0 CMR 00010000 Read FLG 1 CEX? 0 TBF Number of bytes in transmission data > Number of ...
Page 79
Slave data transmission processing routine 2 Fig. 6-10 shows the flow of slave data transmission processing routine 2. Fig. 6-10 Flow of Slave Data Transmission Processing Routine 2 Start I > Number of bytes in tranmission data N Read ...
Page 80
Transmission Processing Routine This routine is executed when TRRQ has been set by the interrupt routine during the execution of master transmission processing routine 1 (see 6.4.4 (1)), master transmission processing routine 2 (see 6.4.4 (2)), or the slave ...
Page 81
Reception Processing Routine This routine is executed when RERQ has been set by the interrupt routine. Fig. 6-12 shows the flow of the reception processing routine. Fig. 6-12 Flow of Reception Processing Routine Start Y J>SIZE ? R N ...
Page 82
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (T A Parameter Symbol Supply voltage Input voltage for logic section V I Output voltage for logic section V O Bus input voltage V BI Bus output voltage V BO ...
Page 83
AC CHARACTERISTICS (T = – Parameter Symbol System clock SCK cycle time t KCY SCK high-level width t KH SCK low-level width t KL Note 1 SI (SIO) setup time t SIK Note 1 SI ...
Page 84
Oscillator circuit (External system clock GND C1 C2 Caution When using system clock oscillator, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influences on the wiring capacitance: • Keep the wiring ...
Page 85
Circuit connected to IEBus Bus Bus PD72042B Remark Protective resistor R Terminating resistor R Load capacitor C Please use the capacitor on the bus line under the capacitance shown in the table below. System clock (f 6 MHz 6.29 MHz ...
Page 86
PACKAGE DRAWING 16-PIN PLASTIC SOP (9.53 mm (375 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition detail ...
Page 87
RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with ...
Page 88
APPENDIX A MAIN DIFFERENCES BETWEEN PD72042A, PD72042B, AND PD6708 Item Product Oscillation frequency ( Operating voltage ( Operating ambient temperature ( IEBus Communication mode Driver/receiver Transmission buffer Reception buffer Note Interface with microcomputer Package ...
Page 89
NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
Page 90
IEBus and Inter Equipment are trademarks of NEC Corporation. The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets ...