UPD72042BGT NEC [NEC], UPD72042BGT Datasheet - Page 25

• Manufacturer Part Number: UPD72042BGT
• Description: LSI DEVICE FOR Inter Equipment Bus (IEBus) PROTOCOL CONTROL
• Manufacturer: NEC [NEC]

3.2.2 Two-Wire Data Transfer (SEL = 0)
(1) Control mode
(2) Data read mode
Remark After reset (RESET) cancellation, the state enabling writing to the register at address 0000B is set.
Caution In control mode, each data item is read every eighth clock pulse. (Data of less than eight clock
Note
Cautions 1. When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore,
When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the
following processing.
1
2
Serial clock counter
Register address setting
Register read/write selection
periods is ignored.)
2. The SIO pin is a CMOS I/O pin. So, be careful to avoid an output collision between the SIO
reset pointer
SIO
the remaining bits of the byte cannot be read; at the next falling edge, a read operation is
performed starting from the next byte in the case of RBF, or from the first bit for other registers.
pin and the microcomputer. Further, a pull-up resistor is required when N-ch open-drain
output of the microcomputer is used. Note that if the last output level is low upon the
termination of read mode, current will flow constantly.
State
SCK
C/D
Note
SIO pin input state
SIO pin output state
SCK
C/D
SIO
(selection of register read)
Control mode
1
Data Sheet S13990EJ3V0DS
A0 A1
A2
W
R
/
A3
A0
A1
D0 D1 D2 D3 D4 D5 D6 D7
A2
Data read mode
A3
PD72042B
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