ex256-ptqg100i Actel Corporation, ex256-ptqg100i Datasheet - Page 14

• Manufacturer Part Number: ex256-ptqg100i
• Description: Fpga Ex Family 4k Gates 256 Cells 250mhz 0.22um Cmos Technology 2.5v 100-pin Tqfp
• Manufacturer: Actel Corporation

Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and
software solution that, in conjunction with Actel
Designer software tools, allows users to examine any of
the internal nets of the device while it is operating in a
prototype or a production system. The user can probe
into an eX device via the PRA and PRB pins without
changing the placement and routing of the design and
without
Explorer II's noninvasive method does not alter timing or
loading effects, thus shortening the debug cycle.
Silicon Explorer II does not require relayout or additional
MUXes to bring signals out to an external pin, which is
necessary when using programmable logic devices from
other suppliers.
Silicon
(asynchronous)
Explorer II attaches to a PC's standard COM port, turning
the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
Table 1-7 • Device Configuration Options for Probe Capability (TRST pin reserved)
Figure 1-13 • Silicon Explorer II Probe Setup
1 -1 0
JTAG Mode
Dedicated
Flexible
Dedicated
Flexible
–
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = High in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
eX Automotive Family FPGAs
signals will not pass through these pins and may cause contention.
Actel’s Designer software.
Explorer
using
or
any
II
66 MHz
TRST
High
High
Low
Low
samples
additional
–
1
(synchronous).
Connection
data
Serial
resources.
Security Fuse Programmed
Additional 16 Channels
at
(Logic Analyzer)
Silicon Explorer II
100 MHz
Silicon
Silicon
Yes
No
No
No
No
v3.2
Connection
Connection
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation.
interconnection between Silicon Explorer II and the
automotive-grade
verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Since these pins are active
during probing, critical signals input through these pins
are not available while probing. In addition, the Security
Fuse should not be programmed because doing so
disables the probe circuitry. It is recommended to use a
70Ω series termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70 Ω series
termination is used to prevent data transmission
corruption during probing and reading back the
checksum.
22 Pin
16 Pin
TMS
TCK
TDO
TDI
PRA
PRB
Probe Circuit Outputs
Probe Circuit Outputs
Probe Circuit Secured
PRA, PRB
User I/O
User I/O
eX
3
3
eX FPGAs
device
2
Figure 1-13
to
Probe Circuit Secured
Probing Unavailable
Probe Circuit Inputs
Probe Circuit Inputs
TDI, TCK, TDO
perform
User I/O
illustrates the
3
in-circuit
2