A1280DX-1CQB ACTEL [Actel Corporation], A1280DX-1CQB Datasheet - Page 8

• Manufacturer Part Number: A1280DX-1CQB
• Description: Integrator Series FPGAs: 1200XL and 3200DX Families
• Manufacturer: ACTEL [Actel Corporation]

such as FIFOs, LIFOs, and RAM arrays. Additionally, unused
SRAM blocks can be used to implement registers for other
logic within the design.
I / O M o d u l e s
The I/O modules provide the interface between the device
pins and the logic array.
I/O module. A variety of user functions, determined by a
library macro selection, can be implemented in the module
(refer to the Macro Library Guide for more information). I/O
modules contain a tri-state buffer, input and output latches
which can be configured for input, output, or bi-directional
pins
Figure 5 • I/O Module
The Integrator Series devices contain flexible I/O structures
where each output pin has a dedicated output enable
control. The I/O module can be used to latch input and/or
output data, providing a fast set-up time. In addition, the
Actel Designer Series software tools can build a D-type
flip-flop using a C-module to register input and/or output
signals.
Actel’s Designer Series development tools provide a design
library of I/O macrofunctions which can implement all I/O
configurations supported by the Integrator Series FPGAs.
R o u t i n g S t r u c t u r e
The Integrator Series architecture uses vertical and
horizontal routing tracks to interconnect the various logic
and I/O modules. These routing tracks are metal
interconnects that may either be of continuous length or
broken into pieces called segments. Varying segment
lengths allows interconnection of over 90% of design tracks
to occur with only two antifuse connections. Segments can
8
From Array
To Array
(Figure
* Can be Configured as a Latch or D Flip-Flop
(Using C-Module)
5).
Q
Q
G/CLK*
G/CLK*
D
D
Figure 5
EN
is a block diagram of the
PAD
Discontinued – v3.0
I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s
be joined together at the ends using antifuses to increase
their lengths up to the full length of the track. All
interconnects can be accomplished with a maximum of four
antifuses.
Horizontal Routing
Horizontal channels are located between the rows of
modules and are composed of several routing tracks. The
horizontal routing tracks within the channel are divided
into one or more segments. The minimum horizontal
segment length is the width of a module pair, and the
maximum horizontal segment length is the full length of the
channel. Any segment that spans more than one-third the
row length is considered a long horizontal segment. A
typical channel is shown in
horizontal routing tracks are used to route signal nets;
dedicated routing tracks are used for the global clock
networks and for power and ground tie-off tracks.
Vertical Routing
Another set of routing tracks run vertically through the
module. Vertical tracks are of three types: input, output, and
long, and are divided into one or more segments. Each
segment in an input track is dedicated to the input of a
particular module; each segment in an output track is
dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom of the
array where edge effects occur. Long Vertical Tracks contain
either one or two segments. An example of vertical routing
tracks and segments is shown in
Figure 6 • Routing Structure
A n t i f us e S t r u c t u r e
An antifuse is a “normally open” structure as opposed to the
normally closed fuse structure used in PROMs or PALs. The
use of antifuses to implement a programmable logic device
results in highly-testable structures as well as efficient
Segmented
Horizontal
Routing
Tracks
Vertical Routing Tracks
Figure
Figure
6.
6. Non-dedicated
Antifuses
Logic
Modules