nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 131

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

P0.6 p0Di 6
P0.5 p0Di 5
P0.4 p0Di 4
P0.3 p0Di 3
P0.2 p0Di 2
P0.1 p0Di 1
P0.0 p0Di 0
Pin
a. Flash SPI interface only activated when PROG is set high, no conflict with runtime operations
b. Connection depends on configuration register CKLFCTL 2:0
c. Connection depends on configuration register CKLFCTL 2:0
UART/
RXD
TIMER0
GPINT1
GPINT0
Conflict exists, use priorities to determine IO allocation
Conflict may exist depending on device configuration. In the case of a conflict, use priorities to determine IO alloca-
tion
CKLFCTL 2:0 = 3'b000: Crystal connected between pin P0.0 and pin P0.1.
CKLFCTL 2:0 = 3'b011: Low-amplitude clock source for CKLF from analog connection pin P0.1.
CKLFCTL 2:0 = 3'b100: Digital clock source for ckLF.
CKLFCTL 2: 0 = 3'b000: Crystal connected between pin P0.0 and pin P0.1.
nRF24LE1 Preliminary Product Specification
17.3.1
The connection map described in this chapter is valid for nRF24LE1 in the 24 pin 4x4 mm package.Pins
P0.0 , P0.2 , P0.4 and P0.6 have two system inputs listed per pin. This means that the input from the pin
is driving both blocks inputs through an AND gate when the pin is configured as an input. Pin P0.5 and
P0.6 are listed with two system outputs, such as p0Do 5 and UART/TXD. In these two cases the Port-
Crossbar also combines the two drivers using an AND gate and lets the AND gate drive the pin if it is con-
figured as an output. The AND gate is chosen since both the UART/TXD and UARAT/RXD signals are high
when idle.
The SMISO pin driver is only enabled when the SCSN pin is active.
Revision 1.1
Inputs Outputs XOSC32K SPI Master
connections
Default
p0Do 6
p0Do 5
UART/
TXD
p0Do 4
p0Do 3
p0Do 2
p0Do 1 CKLF
p0Do 0 CKLF
Pin assignments in package 24 pin 4x4 mm
priority 1
b
c
ana
Table 74. Pin out map for the 24 pin 4x4mm package
priority 2
MMISO in
MMOSI out SMOSI
MSCK
out SSCK
priority 3
SCSN
FCSN
SMISO
FMISO
FMOSI
FSCK
Slave/Flash
Dynamically enabled connections
131 of 191
SPI
a
a
a
a
in OCITDO out W2SCL inout
in
out OCITDI in
out
in OCITMS in
in
in OCITCK in
out
priority 4
OCITO
HW Debug
out W2SDA inout PWM1 out AIN6
priority 5
2-Wire
priority 6
PWM0 out AIN3
PWM
ADC/COMP
priority 7
AIN5
AIN4
AIN2
AIN1
AIN0
ana
ana
ana
ana
ana
ana
ana