LT1175 LINER [Linear Technology], LT1175 Datasheet
LT1175
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LT1175 Summary of contents
Page 1
... Special attention was given to the problem of high temperature operation with micropower operating currents, preventing output voltage rise under no-load conditions. The LT1175 is available in 8-pin PDIP and SO packages, 3-lead SOT- 223 as well as 5-pin surface mount DD and through-hole TO-220 packages ...
Page 2
... SHDN Pin to V Operating Junction Temperature Range LT1175C .............................................. 125 C LT1175I .......................................... – 125 C Ambient Operating Temperature Range LT1175C ................................................ LT1175I ............................................ – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 FRONT VIEW PART NUMBER ...
Page 3
... See the graph in Typical Performance Characteristics for guaranteed limits above 12V. Note 12: Operating at very large input-to-output differential voltages (>15V) with load currents less than 5mA requires an output capacitor with an ESR greater than 1 to prevent low level output oscillations. LT1175 = 3V, I and I tied ...
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... LT1175 W U TYPICAL PERFORMANCE CHARACTERISTICS Typical Current Limit Characteristics 1.0 CURRENT LIMIT CHANGES ONLY SLIGHTLY WITH TEMPERATURE SO CURVES ARE REPRESENTATIVE OF ALL TEMPERATURES 0 TIED TO V LIM2 LIM IN 0.6 I TIED TO V LIM4 IN 0.4 I TIED TO V LIM2 IN 0 OPEN LIM2 LIM4 ...
Page 5
... It can be forced to the input voltage, to ground positive with respect to ground without damage or latchup (see Output Voltage Reversal in Appli- cations Information section). The LT1175 has foldback current limit, so maximum current at the OUTPUT pin is a function of input-to-output voltage. See Typical Perfor- mance Characteristics ...
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... DIV The LT1175 fixed 5V design with the SENSE pin acting as a Kelvin connection to the output. Normally the SENSE pin and the OUTPUT pin are connected directly together, either close to the regulator or at the remote load point. SHUTDOWN ...
Page 7
... LT1175 extremely tolerant of output capacitor selec- tion. Like most low dropout designs which use a collector or drain of the power transistor to drive the output node, the LT1175 uses the output capacitor as part of the overall loop compensation. Older regulators generally required the output capacitor to have a minimum value 100 F, a maximum ESR (Effective Series Resistance ...
Page 8
... This range allows the use of ceramic, solid tantalum, aluminum and film capacitors over a wide range of values. The optimum output capacitor type for the LT1175 is still solid tantalum, but there is considerable leeway in select- ing the exact unit. If large load current transients are expected, larger capacitors with lower ESR may be needed to control worst-case output variation during transients ...
Page 9
... This load absorbs power transistor leakage and maintains good regulation. There is one downside to this feature, however. If the output is pulled high deliberately might be when the LT1175 is used as a backup to a slightly higher output from a primary regulator, the LT1175 will act as an unwanted load on the primary regulator. ...
Page 10
... This voltage will contain high fre- quency ripple that must be rejected by the linear regulator. Special care was taken with the LT1175 to maximize high frequency ripple rejection, but as with any micropower design, rejection is strongly affected by ripple frequency. ...
Page 11
... 0.045 – 0.055 (1.143 – 1.397) +0.008 0.004 –0.004 0.059 (1.499) +0.203 0.102 –0.102 TYP 0.095 – 0.115 (2.413 – 2.921) 0.050 0.012 0.013 – 0.023 (1.270 0.305) (0.330 – 0.584) LT1175 Q(DD5) 0396 11 ...
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... LT1175 PACKAGE DESCRIPTION N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 0.255 0.015* (6.477 0.381 0.300 – 0.325 0.045 – 0.065 (1.143 – 1.651) (7.620 – 8.255) 0.065 (1.651) 0.009 – 0.015 TYP (0.229 – 0.381) +0 ...