LTC1864 LINER [Linear Technology], LTC1864 Datasheet
LTC1864
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LTC1864 Summary of contents
Page 1
... The supply current drops at lower speeds because the LTC1864/LTC1865 automatically power down between conversions. These 16-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1864 has a differential analog input with an adjustable reference pin. The LTC1865 offers a software- selectable 2-channel MUX and an adjustable reference pin on the MSOP version. ...
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... Transition Noise Gain Error 2 U (Notes 1, 2) Operating Temperature Range LTC1864C/LTC1865C/ LTC1864AC/LTC1865AC ........................ 0°C to 70°C LTC1864I/LTC1865I/ + 0.3V) CC LTC1864AI/LTC1865AI ..................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C + 0.3V) CC Lead Temperature (Soldering, 10 sec)................. 300° ORDER PART NUMBER LTC1864CMS8 CONV 1 ...
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... 5V 5V defined in Recommended Operating Conditions, unless otherwise noted. CC REF SCK SCK(MAX) PARAMETER CONDITIONS Offset Error LTC1864 SO-8 and MSOP, LTC1865 MSOP LTC1865 SO-8 + Input Differential Voltage Range Absolute Input Range IN Input – IN ...
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... LTC1864/LTC1865 MIN TYP MAX UNITS 4.75 5.25 ● • SCK + t CONV 40% 1/f 40% 1/f t CONV 16 13 LTC1864/LTC1865 MIN TYP MAX UNITS ● 2.75 3.2 ● 250 15 20 ● 25 ● ● ● sn18645 18645fs ...
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... G05 Typical DNL Curve 25° REF 1 0 –1 –2 0 16384 32768 65536 49152 CODE 1864/65 G08 LTC1864/LTC1865 Sleep Current vs Temperature 1000 CONV = 900 800 700 600 500 400 300 200 100 0 –50 – 100 125 TEMPERATURE (° ...
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... LTC1864/LTC1865 W U TYPICAL PERFOR A CE CHARACTERISTICS Change in Offset Error vs Reference Voltage 25° – REFERENCE VOLTAGE (V) 1864/65 G10 Change in Gain Error vs Temperature REF –1 –2 –3 –4 –5 –50 –25 ...
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... CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. LTC1864/LTC1865 down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin ...
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... LTC1864/LTC1865 U U FUNCTIONAL BLOCK DIAGRA PIN NAMES IN PARENTHESES REFER TO LTC1865 + IN (CH0) – IN (CH1) GND TEST CIRCUITS Load Circuit for dDO r f TEST POINT 3k SDO 20pF Voltage Waveforms for t CONV SDO t en Voltage Waveforms for SDO Delay Times, t SCK dDO ...
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... The LTC1864 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV finished. If CONV is left high after this time, the LTC1864 goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1864 goes into sample mode and SDO is enabled ...
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... LTC1864/LTC1865 U U APPLICATIO S I FOR ATIO LTC1865 OPERATION Operating Sequence The LTC1865 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV finished. If CONV is left high after this time, the LTC1865 goes into sleep mode drawing only leakage current. The LTC1865’ ...
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... Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1864/ LTC1865 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200Ω or high speed op amps are used (e ...
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... LTC1864/LTC1865 U U APPLICATIO S I FOR ATIO sn18645 18645fs ...
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... U U APPLICATIO S I FOR ATIO Component Side Silk Screen for LTC1864 Evaluation Circuit Component Side Showing Traces (Note Wider Traces on Analog Side) Ground Layer with Separate Analog and Digital Grounds W U (Note Almost No Analog Traces on Board Bottom) Supply Layer with 5V Digital Supply and Analog Ground Repeated ...
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... U10 14 LTC1799 Q0 13 100k OUT GND DIV SET 10 ENT 9 LO CLK Figure 6. LTC1864 Manchester Transmitter U11 5V 5V 15V LT1121CST-5 AN DIG R4 2Ω OUT C26 GND 10µF 6.3V 2 1206 5V 5V DIG DIG LTC1485 ...
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... IC2A IC6D IC5C IC4A 74AC74 74AC32 74AC86 74AC08 5 4 PRE CLK 3 CLK 6 1 CLR Q DATA DATA Figure 7. LTC1864 Manchester Receiver LTC1864/LTC1865 IC3A IC2B IC4B 74AC74 74AC74 74AC08 PRE PRE CLK 3 CLK 11 CLK CLK ...
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... With AC family CMOS logic at 5V the receiver clock frequency is limited to 20MHz; the corresponding trans- mitter clock frequency is 2.5MHz. If the receiver is imple- mented in an FPGA that can be clocked at 160MHz, the LTC1864 can be clocked at its rated clock frequency of 20MHz. output of the second IN sn18645 18645fs ...
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... LTC DWG # 05-08-1660) DETAIL “A” 0.254 (.010) 0° – 6° TYP GAUGE PLANE 0.53 ± 0.015 (.021 ± .006) DETAIL “A” 0.18 (.077) SEATING LTC1864/LTC1865 3.00 ± 0.102 (.118 ± .004) 0.52 (.206) (NOTE REF 3.00 ± 0.102 4.88 ± 0.1 (.118 ± .004) (.192 ± ...
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... LTC1864/LTC1865 PACKAGE DESCRIPTIO 0.889 ± 0.127 (.035 ± .005) 5.23 3.2 – 3.45 (.206) (.126 – .136) MIN 0.305 ± 0.038 0.50 (.0120 ± .0015) (.0197) TYP BSC RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. ...
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... TYP 0.014 – 0.019 (0.355 – 0.483) TYP LTC1864/LTC1865 0.150 – 0.157** (3.810 – 3.988) SO8 1298 0.004 – 0.010 (0.101 – 0.254) ...
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... REF 100pF 0.1µ REF SCK LTC1864 SDO IN – 5 CONV 3 GND 4 100Ω 100pF POWER DISSIPATION DESCRIPTION 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference ±5V 15mW Serial/Parallel I/O, Internal Reference ±5V 65mW Configurable Bipolar or Unipolar Input Ranges, 5V Bandgap, 130µ ...