LTC1923 LINER [Linear Technology], LTC1923 Datasheet - Page 16

• Manufacturer Part Number: LTC1923
• Description: High Efficiency Thermoelectric Cooler Controller
• Manufacturer: LINER [Linear Technology]

LTC1923
OPERATIO
If the external frequency (f
lator frequency, current is sourced continuously out of the
PLLLPF pin. When the external frequency is less than the
oscillator frequency, current is sunk by the PLLLPF pin.
The loop filter components R
current pulses from the phase detector and provide a
stable input to the VCO. These components also determine
how fast the loop acquires lock. In most instances C
can be omitted, R
selected to be 0.01 F to 0.1 F to stabilize the loop. Make
sure that the low side of filter components is tied to AGND
to keep unwanted switching noise from altering the perfor-
mance of the PLL.
Figure 9 illustrates three different ways to set the oscilla-
tor frequency. In Figure 9a, the oscillator is free running
with the frequency determined by R
16
Figure 9. Oscillator Frequency Setup: a) Free Running b) Slaved Operation c) Master/Slave Operation
V
NC
DD
U
LP
(9c) Master/Slave Operation—Set Oscillator Frequency of Slave at 70% to 80% of Master
(9a) Free Running
can be set to 1k and C
PLLLPF
SDSYNC
PLLIN
LTC1923
LP
FREQUENCY
, C
EXTERNAL
1923 F09a
R
C
) is greater than the oscil-
T
T
RPLL
LP
V
T
DD
and C
and C
R
R
PLL
SDSYNCB
T
C
T
Figure 8. Phase-Locked Loop Block Diagram
PLLLPF
SDSYNC
V
LP2
DD
T
MASTER
LTC1923
. In Figure 9b,
, smooth out
LP
R
C
T
T
FREQUENCY
DETECTOR
DIGITAL
PHASE
can be
LP2
R
T
C
T
V
DD
CLP2
the oscillator is slaved to an external clock. Figure 9c
illustrates how one LTC1923 can be used as a master to
synchronize other LTC1923s or additional devices requir-
ing synchronization. To implement this, determine the
values of R
oscillator frequency of the master by using the equation
given in the oscillator frequency section. Tie the master’s
PLLLPF pin to V
resistor R
set to 10k, but may need to be a lower value if higher
frequency operation is desired (above 250kHz). Set the
slave free-running frequencies to be 20% to 30% less
than this. The SDSYNC pin of the master will switch at its
free-running frequency (with approximately 50% duty
cycle), and this can be used to synchronize the other
devices.
PLLLPF
(9b) Slave Operation with External Clock—
Set Oscillator Frequency at 70% to 80% of External Clock
RLP
R
CLP
LP
C
LP
PLL
PLLLPF
SDSYNC
T
as shown in Figure 9c. R
CLP2
LTC1923
and C
C
SLAVE
LP2
DD
OSC
1923 F09c
CLKIN
R
C
and the SDSYNC pin to V
T
T
T
1923 F08
to obtain the desired free-running
RLP
CLP
R
C
1.2 • R
T
T
C
PLLLPF
SDSYNC
T
LTC1923
T
1923 F09b
R
C
T
T
PLL
R
typically can be
T
C
T
DD
through a
1923f