TFA9812HN PHILIPS [NXP Semiconductors], TFA9812HN Datasheet - Page 26
TFA9812HN
Manufacturer Part Number
TFA9812HN
Description
BTL stereo Class-D audio amplifier with I2S input
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.TFA9812HN.pdf
(66 pages)
- Current page: 26 of 66
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NXP Semiconductors
TFA9812_2
Preliminary data sheet
8.7.11 Invalid BCK protection
8.7.12 DC blocking
8.7.13 Overview protections
The BCK clock signal is verified as being at one of the allowed relative frequencies: 32 f
48 f
to 3-state mode to prevent audible effects.
The MCLK clock signal is also verified as being valid, see
Detection of violation results in an automatic internal overruling of the MCLK assignment
to BCK.
The TFA9812 features a high pass filter after the I
at the output can damage the peripheral devices. The high pass filter is always enabled.
Table 21
Table 21.
Protections
Symbol Conditions
TF
OTP
OCP
OVP
UVP
ODP
WP
LP
UFP
s
[2]
or 64 f
shows the overview of the protections.
programmable
max. T
T
I
V
V
V
T
OUTX > V
OUTX < REFA + 1 V
PLL out of lock
PLL frequency < 45 MHz
O
Overview protections
j
j
DDA
DDA
DDA(3V3)
s
> 160 C
> 140 C and I
> I
. If it is not at one of these frequencies the TFA9812 will set the output stages
ORM
> 20 V
< 8 V or
j
> 125 C
< 3 V
DDA
Rev. 02 — 22 January 2009
1 V or
O
> I
ORM
DIAG
pin
Floating
LOW
LOW
LOW
LOW
LOW
LOW
Floating
Floating
BTL stereo Class-D audio amplifier with I
I
flag
-
DIAG
DIAG
DIAG
DIAG
DIAG
DIAG
LP
UFP
2
C
[1]
2
S input to block DC signals. DC values
Output
Switching Automatic, increasing
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Section
Recovering
volume control back to
volume setting
Automatic, after 1 s and
T
Automatic, after 1 s and
I
Restart (fault to operating
when V
V
Restart (fault to operating
when V
V
Restart (fault to operating
when T
IO < I
Restart (fault to operating
when OUTX < V
and OUTX > V
Restart (fault to operating
when PLL is in lock)
Restart (fault to operating
when
PLL frequency > 45 MHz)
O
j
DDA(3V3)
DDA(3V3)
< 160 C
< I
8.2.3.
ORM
ORM
DDA
DDA
j
< 140 C or
© NXP B.V. 2009. All rights reserved.
TFA9812
)
> 3 V)
> 3 V)
> 8 V and
> 8 V and
SSA
DDA
+ 1 V)
2
S input
26 of 66
1 V
s
,
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