PI6C2409 Pericom Semiconductor Corporation, PI6C2409 Datasheet
PI6C2409
Manufacturer Part Number
PI6C2409
Description
Zero-Delay Clock Buffer
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI6C2409.pdf
(8 pages)
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1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Product Features
Block Diagram
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 200ps
Internal feedback allows outputs to be synchronized
to the clock input
Operates at 3.3V V
Space-saving Packages:
150-mil SOIC (W)
173-mil TSSOP (L)
CLKIN
PI6C2409(-1, -1H)
SEL1
SEL2
Decode
Logic
DD
PLL
MUX
OUT0
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
1
Functional Description
The PI6C2409 is a PLL based, zero-delay buffer, with the ability
to distribute nine outputs of up to 133MHz at 3.3V.
All the outputs are distributed from a single clock input CLKIN and
output OUT0 performs zero delay by connecting a feedback to PLL.
PI6C2409 has two banks of four outputs that can be controlled by
the selection inputs, SEL1 & SEL2. It also has a powersparing feature:
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all
outputs are referenced from CLKIN. PI6C2409 is available in
high drive and industrial environment versions.
An internal feedback on OUT0 is used to synchronize the
outputs to the input; the relationship between loading of this signal
and the outputs determines the input-output delay.
PI6C2409 are characterized for both commercial and
industrial operation
Pin Configuration
OUTA1
OUTA2
OUTB1
OUTB2
CLKIN
SEL2
GND
V DD
1
2
3
4
5
6
7
8
Zero-Delay Clock Buffer
16-Pin
W, L
16
15
14
13
12
11
10
9
OUT0
OUTA4
OUTA3
V DD
GND
OUTB4
OUTB3
SEL1
PI6C2409
PS8613A
07/15/03
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PI6C2409 Summary of contents
Page 1
... All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. PI6C2409 has two banks of four outputs that can be controlled by the selection inputs, SEL1 & SEL2. It also has a powersparing feature: when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all outputs are referenced from CLKIN ...
Page 2
... PI6C2409 PS8613A 07/15/03 ...
Page 3
... Zero Delay Clock Buffer PI6C2409-1H PI6C2409 – PS8613A PI6C2409 25 +0. º 07/15/03 ...
Page 4
... – PI6C2409 ...
Page 5
... – PI6C2409 ...
Page 6
... CLK out C LOAD 0.1µF Test Circuit for t SLEW 6 Zero Delay Clock Buffer t low high high+ t low 3.3V 2.0V 0. Test Circuit 1kΩ OUTPUTS 1kΩ GND GND , Output slew rate on –1H device SLEW PI6C2409 CLK out 10pF PS8613A 07/15/03 ...
Page 7
... X.XX DENOTES DIMENSIONS 0.508 X.XX IN MILLIMETERS .169 4.3 .177 4.5 .047 max. 1.20 SEATING PLANE .002 0.05 .006 0.15 X.XX X.XX 7 Zero Delay Clock Buffer 0.25 .0099 x 45˚ 0.50 .0196 0.19 .0075 .0098 0.25 0.41 .016 1.27 .050 .2284 .2440 5.80 6.20 .004 .008 0.45 .018 0.75 .030 .252 BSC 6.4 DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS PI6C2409 0.09 0.20 PS8613A 07/15/03 ...
Page 8
... Zero Delay Clock Buffer PS8613A PI6C2409 07/15/03 ...