AD7226 Analog Devices, AD7226 Datasheet - Page 6

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AD7226

Manufacturer Part Number
AD7226
Description
LC2MOS Quad 8-Bit D/A Converter
Manufacturer
Analog Devices
Datasheet

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AD7226
INTERFACE LOGIC INFORMATION
Address lines A0 and A1 select which DAC will accept data
from the input port. Table I shows the selection table for the
four DACs with Figure 4 showing the input control logic. When
the WR signal is LOW, the input latches of the selected DAC
are transparent and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high the analog outputs remain
at the value corresponding to the data held in their respective
latches.
AD7226 Control Inputs
WR
H
L
g
L
g
L
g
L
g
L = Low State, H = High State, X = Don’t Care
A1
X
L
L
L
L
H
H
H
H
Figure 5. Write Cycle Timing Diagram
Figure 4. Input Control Logic
Table I. AD7226 Truth Table
A0
X
L
L
H
H
L
L
H
H
AD7226
Operation
No Operation Device Not Selected
DAC A Transparent
DAC A Latched
DAC B Transparent
DAC B Latched
DAC C Transparent
DAC C Latched
DAC D Transparent
DAC D Latched
–6–
Typical Performance Characteristics
(T
A
= 25 C, V
Figure 8. Differential Nonlinearity vs. V
Figure 6. Channel-to-Channel Matching
DD
Figure 7. Relative Accuracy vs. V
= +15 V, V
SS
= –5 V)
REF
REF
REV. A

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