M29W400 ST Microelectronics, M29W400 Datasheet - Page 10

• Manufacturer Part Number: M29W400
• Description: 4 Mbit 512Kb x8 or 256Kb x16 / Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: ST Microelectronics

M29W400T, M29W400B
Table 8. Instructions
Notes: 1. Commands not interpreted in this table will default to read array mode.
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand executionwill automaticallyoutput these five
Status Register bits. The P/E.C. automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
10/34
RD
ES
Mne.
AS
PG
BE
CE
ER
(2,4)
(10)
(4)
2. A wait of t
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
5. Signature Address bits A0, A1 at V
6. Block Protection Address: A0 at V
7. For Coded cycles address inputs A15-A17 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend,Read and Data Program functions are allowed in blocks not being erased.
before starting any new operation (see Table 14 and Figure 9).
the command cycles.
Device code.
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or
Toggle bit until Erase is completed or suspended.
Read/Reset
Memory Array
Auto Select
Program
Block Erase
Chip Erase
Erase
Suspend
Erase
Resume
Instr.
PLYH
is necessary after a Read/Reset command if the memory was in an Erase or Program mode
Cyc.
1+
3+
3+
4
6
6
1
1
(1)
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
(3,7)
(3,7)
(3,7)
(3,7)
(3,7)
(3,7)
(3,7)
(3,7)
IL
IL
, A1 at V
will output Manufacturer code (20h). Address bits A0 at V
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
IH
and A12-A17 within the Block will output the Block Protection status.
1st Cyc.
AAAAh
AAAAh
AAAAh
AAAAh
AAAAh
5555h
5555h
5555h
5555h
5555h
AAh
AAh
AAh
AAh
AAh
B0h
F0h
30h
X
X
X
Read Memory Array until a new write cycle is initiated.
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or Erase is
suspended another time
2nd Cyc. 3rd Cyc.
2AAAh
2AAAh
2AAAh
2AAAh
2AAAh
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation,DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
5555h
5555h
5555h
5555h
5555h
55h
55h
55h
55h
55h
AAAAh
AAAAh
AAAAh
AAAAh
AAAAh
5555h
5555h
5555h
5555h
5555h
F0h
90h
A0h
80h
80h
Read Memory Array until a new write cycle
is initiated.
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
Program
4th Cyc.
Program
Address
AAAAh
AAAAh
5555h
5555h
Data
AAh
AAh
IH
Read Data Polling or Toggle Bit
until Program completes.
and A1 at V
5th Cyc.
2AAAh
2AAAh
5555h
5555h
55h
55h
IL
6th Cyc.
Address
AAAAh
Block
5555h
will output
30h
10h
Additional
7th Cyc.
Block
Note 9
30h
(8)