SY89425 Micrel Semiconductor, SY89425 Datasheet - Page 3

• Manufacturer Part Number: SY89425
• Description: DUAL SONET OC-12 CLOCK SYNTHESIZER
• Manufacturer: Micrel Semiconductor

NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
Micrel
INPUTS
RFCKB [Reference Clock B] TTL
Reference clock in for PLL B. (38.88, 51.84 or 77.76MHz).
SEL39B [38.88MHz Select B] TTL
Logic HIGH on this pin denotes a 38.88MHz input reference
clock for PLL B. Tie to logic LOW if input is not 38.88MHz.
SEL78B [77.76MHz Select B] TTL
Logic HIGH on this pin denotes a 77.76MHz input reference
clock for PLL A. Tie to logic LOW if input is not 77.76MHz.
RSTB [Reset B] TTL
Tie to logic LOW for normal operation; logic HIGH forces reset
of internal Phase Detector & feedback dividers on PLL B.
FLTRBP, FLTRBN (Loop Filter B, Pos & Neg) Analog.
Connect a series RC loop filter between these pins. The
suggested loop filter is 0.1 F and 500 ohms, as shown in the
typical application on page 3-9.
RSTA (Reset A) TTL
Tie to logic LOW for normal operation; logic HIGH forces reset
of internal Phase Detector & feedback dividers on PLL A.
SEL78A [77.76MHz Select A] TTL
Logic HIGH on this pin denotes a 77.76MHz input reference
clock for PLL A. Tie to logic LOW if input is not 77.76MHz.
SEL39A [38.88MHz Select A] TTL
Logic HIGH on this pin denotes a 38.88MHz input reference
clock for PLL A. Tie to logic LOW if input is not 38.88MHz.
ABSOLUTE MAXIMUM RATINGS
PIN DESCRIPTION
V
V
I
T
T
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
OUT
CC
I
A
store
Symbol
Power Supply
Input Voltage
Output Current
Operatimg Temperature Range
Storage Temperature Range
(1)
Parameter
–Continuous
–Surge
3
REFCKA [Reference Clock A] TTL
Reference clock in for PLL A.
FLTRAP, FLTRAN (Loop Filter A, Pos & Neg) Analog.
Connect a series RC loop filter between these pins. The
suggested loop filter is 0.1 F and 500 ohms, as shown in the
typical application on page 5-527.
OUTPUTS
CK622BP, CK622BN (Clock Out B) Differential PECL
622.08MHz output clock from PLL B.
CK622AP, CK622AN (Clock Out A)
622.08MHz output clock from PLL A.
POWER & GROUND
V
V
V
V
GND
CCA
CCB
CCOA
CCOB
REFERENCE FREQUENCY SELECTION
SEL39
0
0
1
1
+5V for PLL A.
+5V for PLL B.
+5V for PLL A PECL outputs.
+5V for PLL B PECL outputs.
Ground (0 volts)
–65 to +150
0 to V
0 to +85
Rating
0 to +7
SEL78
100
50
0
1
0
1
CC
Differential PECL
fRFCK
ClockWorks™
51.84
77.76
38.88
77.76
Unit
mA
V
V
C
C
SY89425