74LVC161 Philips, 74LVC161 Datasheet - Page 2

• Manufacturer Part Number: 74LVC161
• Description: Presettable synchronous 4-bit binary counter; asynchronous reset
• Manufacturer: Philips

1. C
2. The condition is V
FEATURES
DESCRIPTION
The 74LVC161 is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
Philips Semiconductors
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1998 May 20
SYMBOL
t
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8–1A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Asynchronous reset
Synchronous counting and loading
Two count enable inputs for n–bit cascading
Positive edge–triggered clock
Output drive capability 50 W transmission lines @85_C
Presettable synchronous 4-bit binary counter;
asynchronous reset
PHL
P
f
f
i
o
f
C
MAX
PD
D
= input frequency in MHz; C
(C
C
= output frequency in MHz; V
PD
/t
= C
I
PLH
L
is used to determine the dynamic power dissipation (P
x V
PD
amb
CC
PACKAGES
x V
2
= 25 C; T
CC
x f
Propagation delay
CP to Q
CP to TC
MR to Q
MR to TC
CET to TC
maximum clock frequency
input capacitance
power dissipation capacitance per gate
o )
2
x f
1
= sum of the outputs
= GND to V
i
+ (C
n
R
n
= T
L
F
x V
PARAMETER
L
 2.5ns
= output load capacity in pF;
CC
CC
CC
2
= supply voltage in V;
TEMPERATURE RANGE
x f
o )
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
where:
D
in W)
OUTSIDE NORTH AMERICA
2
The 74LVC161 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for
high–speed counting. Synchronous operation is provided by having
all flip–flops clocked simultaneously on the positive–going edge of
the clock (CP). The outputs (Q
preset to a HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the data at the
data inputs (D
positive–going edge of the clock (provided that the set–up and hold
time requirements for PE are met). Preset takes place regardless of
the levels at count enable inputs (CEP and CET). A low level at the
master reset input (MR) sets all four outputs of the flip–flops
(Q
and CEP inputs (thus providing an asynchronous clear function).
The look–ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set–up time,
according to the following formula:
74LVC161 PW
74LVC161 DB
f
max
74LVC161 D
0
=
to Q
CONDITIONS
notes 1 and 2
_______________________________
3
V
tp
C
) to LOW level regardless of the levels at CP, PE, CET
CC
L
(max)
= 50 pF
0
= 3.3V
to D
(CP to TC) + t
3
) to be loaded into the counter on the
NORTH AMERICA
74LVC161PW DH
1
74LVC161 DB
74LVC161 D
0
SU
to Q
(CEP to CP)
3
) of the counters may be
TYPICAL
Product specification
200
4.9
5.7
5.2
5.7
4.5
5.0
39
74LVC161
DWG NUMBER
853-1864 19421
SOT109-1
SOT338-1
SOT403-1
UNIT
MHz
pF
pF
ns
0
. This