M41T315W-65MH6TR ST Microelectronics, M41T315W-65MH6TR Datasheet - Page 7

• Manufacturer Part Number: M41T315W-65MH6TR
• Description: Serial Access Phantom RTC Supervisor
• Manufacturer: ST Microelectronics

OPERATION
Figure 6., page 5
the device. The following paragraphs describe the
signals and functions.
Communication with the clock is established by
pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecu-
tive WRITE cycles containing the proper data on
data in (D). All accesses which occur prior to rec-
ognition of the 64-bit pattern are directed to mem-
ory via the chip enable output pin (
After recognition is established, the next 64 READ
or WRITE Cycles either extract or update data in
the clock and
disabling the connected memory (see
2., page
Data transfer to and from the timekeeping function
is accomplished with a serial bit stream under con-
trol of chip enable input (
and WRITE enable (
using the
pattern recognition sequence by moving the point-
er to the first bit of the 64-bit comparison register.
Next, 64 consecutive WRITE cycles are executed
using the
64 WRITE cycles are used only to gain access to
the clock.
When the first WRITE cycle is executed, it is com-
pared to the first bit of the 64-bit comparison reg-
Table 2. Operating Modes
Note: X = V
Note: 1. See
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
7).
IH
CEI
CEI
Table 11., page 17
or V
V
and
IL
and
CEO
SO
; V
SO
4.5 to 5.5V
3.0 to 3.6V
2.7 to 3.3V
to V
OE
illustrates the main elements of
WE
remains high during this time,
= Battery Back-up Switchover Voltage.
V
V
PFD
WE
control of the clock starts the
or
or
SO
CC
control of the clock. These
(1)
). Initially, a READ cycle
(min)
CEI
for details.
), output enable (
(1)
CEO
CEI
V
V
V
V
X
X
IH
IL
IL
IL
).
Table
OE
V
V
X
X
X
X
OE
IH
IL
),
WE
V
V
V
X
X
X
ister. If a match is found, the pointer increments to
the next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all the bits
in the comparison register have been matched
(see
With a correct match for 64 bits, access to the reg-
isters is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64
cycles will cause the device to either receive data
on D, or transmit data on Q, depending on the lev-
el of
outside the memory block can be interleaved with
CEI
tion sequence or data transfer sequence to the de-
vice.
For a SO16 pin package, a standard 32.768 kHz
quartz crystal can be directly connected to the
M41T315Y/V/W via pins 1 and 2 (XI, XO). The
crystal selected for use should have a specified
load capacitance (C
10., page
IH
IH
IL
cycles without interrupting the pattern recogni-
OE
Figure 10., page
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
M41T315Y*, M41T315V, M41T315W
pin or the
D
IN
17).
D
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
WE
OUT
Q
pin. Cycles to other locations
L
11.)
) of 12.5 pF (see
Battery Back-up Mode
CMOS Standby
Standby
Power
Active
Active
Active
Table
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