PCA8565TS Philips Semiconductors, PCA8565TS Datasheet - Page 13

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PCA8565TS

Manufacturer Part Number
PCA8565TS
Description
Real time clock/calender
Manufacturer
Philips Semiconductors
Datasheet

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Product data
Fig 9. Acknowledgement on the I
Fig 10. Slave address.
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
9.5.1 Addressing
BY RECEIVER
9.5 I
SCL FROM
MASTER
clock pulse. A slave receiver which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must generate an acknowledge
after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end of data to the transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In
this event the transmitter must leave the data line HIGH to enable the master to
generate a stop condition.
Before any data is transmitted on the I
addressed first. The addressing is always carried out with the first byte transmitted
after the start procedure.
The PCA8565 acts as a slave receiver or slave transmitter. Therefore the clock signal
SCL is only an input signal, but the data signal SDA is a bidirectional line.
The PCA8565 slave address is shown in
2
C-bus protocol
condition
2
START
C-bus.
S
1
Rev. 01 — 31 March 2003
group 1
0
1
1
0
0
group 2
2
0
1
2
C-bus, the device which should respond is
MCE189
R/W
Figure
not acknowledge
acknowledge
10.
8
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
acknowledgement
clock pulse for
Real time clock/calender
9
MBC602
PCA8565
13 of 26

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