PCA8565TS Philips Semiconductors, PCA8565TS Datasheet - Page 4

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PCA8565TS

Manufacturer Part Number
PCA8565TS
Description
Real time clock/calender
Manufacturer
Philips Semiconductors
Datasheet

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Product data
8.1 Alarm function modes
8.2 Timer
8.3 CLKOUT output
8.4 Reset
8.5 Voltage-low detector
By clearing the MSB of one or more of the alarm registers (bit AE = alarm enable),
the corresponding alarm condition(s) will be active. In this way an alarm can be
generated from once per minute up to once per week. The alarm condition sets the
Alarm Flag (AF). The asserted AF can be used to generate an interrupt (INT).
The AF can only be cleared by software.
The 8-bit countdown timer at address 0FH is controlled by the timer control register at
address 0EH. The timer control register determines one of 4 source clock
frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or
the timer. The timer counts down from a software-loaded 8-bit binary value. At the
end of every countdown, the timer sets the Timer Flag (TF). The TF may only be
cleared by software. The asserted TF can be used to generate an Interrupt (INT). The
interrupt may be generated as a pulsed signal every countdown period or as a
permanently active signal which follows the condition of TF. Bit TI/TP is used to
control this mode selection. When reading the timer, the current countdown value is
returned.
A programmable square wave is available at pin CLKOUT. Operation is controlled by
the CLKOUT control register at address 0DH. Frequencies of 32.768 kHz (default),
1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock,
microcontroller clock, input to a charge pump, or for calibration of the oscillator.
CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes
high-impedance.
The PCA8565 includes an internal reset circuit which is active whenever the oscillator
is stopped. In the reset state the I
the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC
and AE which are set to logic 1.
The PCA8565 has an on-chip voltage-low detector. When V
bit VL in the seconds register is set to indicate that the integrity of the clock
information is no longer guaranteed. The VL flag can only be cleared by software.
Bit VL is intended to detect the situation when V
under battery operation. Should V
bit VL will be set. This will indicate that the time may be corrupted.
Rev. 01 — 31 March 2003
2
DD
C-bus logic is initialized and all registers, including
reach V
low
DD
before power is re-asserted then
is decreasing slowly, for example
1
60
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Hz), and enables or disables
Real time clock/calender
DD
drops below V
PCA8565
low
4 of 26
,

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