CS51311GD14 Cherry Semiconductor Corporation, CS51311GD14 Datasheet - Page 11

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CS51311GD14

Manufacturer Part Number
CS51311GD14
Description
Synchronous CPU Buck Controller for 12V and 5V Applications
Manufacturer
Cherry Semiconductor Corporation
Datasheet
where
The actual output voltage deviation due to ESR can then be
verified and compared to the value assigned by the design-
er:
Similarly, the maximum allowable ESL is calculated from
the following formula:
where
The actual maximum allowable ESL can be determined by
using the equation:
where ESL
ed that a 10 × 12mm Aluminum Electrolytic capacitor has
approximately 4nH of package inductance).
The actual output voltage deviation due to the actual maxi-
mum ESL can then be verified:
The designer now must determine the change in output
voltage due to output capacitor discharge during the tran-
sient:
where
The total change in output voltage as a result of a load cur-
rent transient can be verified by the following formula:
Step 3: Selection of the Duty Cycle,
Switching Frequency, Switch On-Time (T
and Switch Off-Time (T
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
ESR
manufacturer’s data sheet);
ESR
∆I/∆T = load current slew rate (as high as 20A/µs);
∆V
∆t
(assigned by the designer);
∆V
tor discharge;
∆I = Load step.
TR
ESL
CAP
CAP
MAX
= the output voltage transient response time
ESL
= change in output voltage due to ESL.
= output voltage deviation due to output capaci-
= maximum ESR per capacitor (specified in
CAP
= maximum allowable ESR.
Number of capacitors =
MAX
∆V
= maximum ESL per capacitor (it is estimat-
OUT
=
∆V
ESL
∆V
∆V
Number of output capacitors
ESR
= ∆V
ESL
CAP
MAX
= ∆I
=
OFF
ESR
=
=
ESL
OUT
)
+ ∆V
∆V
∆I × ∆t
ESL
MAX
C
× ESR
ESL
∆t
OUT
∆I
ESL
CAP
× ∆t
× ∆I
TR
ESR
ESR
+ ∆V
MAX
,
,
.
MAX
CAP
Application Information: continued
CAP
ON
)
,
,
11
where
Step3a: Calculation of Switch On-Time
The switch On-Time (time during which the switching
MOSFET in a synchronous buck topology is conducting) is
determined by:
where F
designer.
Higher operating frequencies allow the use of smaller
inductor and capacitor values. Nevertheless, it is common
to select lower frequency operation because a higher fre-
quency results in lower efficiency due to MOSFET gate
charge losses. Additionally, the use of smaller inductors at
higher frequencies results in higher ripple current, higher
output voltage ripple, and lower efficiency at light load
currents.
Step 3b: Calculation of Switch Off-Time
The switch Off-Time (time during which the switching
MOSFET is not conducting) can be determined by:
The C
the Off-Time, T
where
Step 4: Selection of the Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the induc-
tor value will decrease output voltage ripple, but degrade
transient response. There are many factors to consider in
selecting the inductor including cost, efficiency, EMI and
ease of manufacture. The inductor must be able to handle
the peak current at the switching frequency without satu-
rating, and the copper resistance in the winding should be
kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic
cores that could be used for this application. Among them
are ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. Powdered iron cores are very com-
monly used. Powdered iron cores are very suitable due to
V
V
V
DC resistance;
V
V
V
3980 is a characteristic factor of the CS51311;
D = Duty Cycle.
OUT
HFET
L
DROOP
IN
LFET
Duty Cycle = D =
= output inductor voltage drop due to inductor wire
OFF
= buck regulator input voltage;
= buck regulator output voltage;
SW
= low side FET voltage drop due to R
= high side FET voltage drop due to R
capacitor value has to be selected in order to set
= droop (current sense) resistor voltage drop;
= regulator switching frequency selected by the
OFF
C
OFF
, above:
T
T
ON
OFF
=
V
=
OUT
Period × (1 − D)
=
V
Duty Cycle
IN
F
+ (V
SW
1
+ V
F
3980
SW
− T
HFET
LFET
ON
− V
+ V
,
,
HFET
L
,
+ V
DS(ON)
− V
DROOP
DS(ON)
L
.
)
;
,

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