ADV7120KN30 Analog Devices, ADV7120KN30 Datasheet - Page 7

• Manufacturer Part Number: ADV7120KN30
• Description: CMOS 80 MHz/ Triple 8-Bit Video DAC
• Manufacturer: Analog Devices

REV. B
If we, therefore, have a graphics system with a 1024 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Video Synchronization and Control
The ADV7120 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The I
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV7120’s analog outputs, the SYNC in-
put should be tied to logic low and the I
nected to analog ground.
Dot Rate = 1024
SYNC
Description
WHITE LEVEL
WHITE LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
NOTE
Typical with full-scale IOG = 26.67 mA.
V
current output is typically connected directly to the
REF
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75
2. V
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
= 78.6 MHz
= 1.235 V, R
19.05
RED, BLUE
mA
1.44
REF
0
= 1.235V, R
0.714
0.054
V
1024
0
SET
SET
= 560 , I
26.67
mA
9.05
7.62
0
= 560 , I
GREEN
60/0.8
IOG
video + 9.05
video + 1.44
7.62
0
(mA)
26.67
26.67
9.05
1.44
1.000
0.340
0.286
SYNC
SYNC
V
0
SYNC
l
connected to IOG.
CONNECTED TO IOG.
Figure 3. RGB Video Output Waveform
should be con-
Table I. Video Output Truth Table
92.5 IRE
7.5 IRE
40 IRE
IOR, IOB
(mA)
19.05
19.05
video + 1.44
video + 1.44
1.44
1.44
0
0
LOAD.
–7–
0
0
0
REF
WHITE
1
0
0
0
0
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7120
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7120 be driven by a TTL buffer (e.g.,
74F244).
Reference Input
An external 1.23 V voltage reference is required to drive
the ADV7120. The AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost,
temperature compensated bandgap voltage reference which
provides a fixed 1.23 V output voltage for input currents
between 50 A and 5 mA. Figure 4 shows a typical refer-
ence circuit connection diagram. The voltage reference gets
its current drive from the ADV7120’s V
board 1 k resistor to the V
pacitor is required between the COMP pin and V
This is necessary so as to provide compensation for the
internal reference amplifier.
SYNC
1
1
1
0
1
0
1
0
1
0
BLANK
1
1
1
1
1
0
REF
pin. A 0.1 F ceramic ca-
DAC
Input Data
xxH
FFH
data
xxH
xxH
data
00H
00H
AA
BLACK LEVEL
BLANK LEVEL
WHITE LEVEL
SYNC LEVEL
through an on-
ADV7120
AA
.