ADV7177 Analog Devices, ADV7177 Datasheet - Page 22

• Manufacturer Part Number: ADV7177
• Description: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
• Manufacturer: Analog Devices

ADV7177/ADV7178
The ADV7177/ADV7178 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7178 has 36
subaddresses and the ADV7177 has 31 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allows data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high pe-
riod, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7177/ADV7178 will not issue an acknowledge and will
return to the idle condition. If, in auto-increment mode, the
user exceeds the highest subaddress, the following action will be
taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
SEQUENCE
SEQUENCE
WRITE
READ
S
S
S = START BIT
P = STOP BIT
SLAVE ADDR A(S)
SLAVE ADDR A(S)
LSB = 0
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
SUB ADDR
SUB ADDR
Figure 30. Write and Read Sequences
A(S)
A(S) S SLAVE ADDR A(S)
DATA
–22–
LSB = 1
2. In Write Mode, the data for the invalid byte will not be
Figure 29 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7177/
ADV7178 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
SCLOCK
SDATA
A(S)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7177/ADV7178 and the part will re-
turn to the idle condition.
START ADDR R/W ACK SUBADDRESS ACK
S
DATA
1-7
Figure 29. Bus Data Transfer
DATA
8
A(M)
9
A(S) P
1-7
DATA
8
9
A(M)
1-7
DATA
P
8
ACK
9
REV. 0
STOP
P