ADV7177 Analog Devices, ADV7177 Datasheet - Page 26

• Manufacturer Part Number: ADV7177
• Description: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
• Manufacturer: Analog Devices

ADV7177/ADV7178
TIMING REGISTER 1 (TR17–TR10)
(Address [SR4–SR0] = 0CH)
Timing Register 1 is an 8-bit-wide register.
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Delay Control (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
VSYNC Width (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 2, these bits
adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 0DH)
Mode Register 2 is an 8-bit-wide register.
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR27
LOW POWER
0
1
MODE
MR27
DISABLE
ENABLE
MR26
0
1
CONTROL
RGB/YUV
RGB OUTPUT
YUV OUTPUT
MR26
MR25
0
1
ENABLE BURST
DISABLE BURST
CONTROL
BURST
MR25
Figure 39. Mode Register 2
MR24
0
1
CHROMINANCE
CONTROL
ENABLE COLOR
DISABLE COLOR
MR24
–26–
MR23
0
1
CCIR624/CCIR601
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
Active Video Line Control (MR23)
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
MR06
0
0
1
1
CVBS: Composite Video Baseband Signal
Y:
C:
U:
V:
R:
G:
B:
Low Power Control (MR27)
This bit enables the lower power mode of the ADV7177/
ADV7178. This will reduce DAC current by 50%.
CONTROL
CCIR624 OUTPUT
CCIR601 OUTPUT
MR23
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
Table II. DAC Output Configuration Matrix
MR22
ZERO SHOULD
BE WRITTEN TO
THESE BITS
MR26
0
1
0
1
MR22–MR21
(00)
MR21
DAC A
CVBS
CVBS
B
U
MR20
SQUARE PIXEL
0
1
MR20
CONTROL
DISABLE
ENABLE
DAC B
Y
Y
S
Y
DAC C
C
C
R
V
REV. 0