X9251 Xicor, X9251 Datasheet
X9251
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X9251 Summary of contents
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... V SS REV 1.3.3 2/10/04 S YSTEM X9251 TM DESCRIPTION The X9251 integrates four digitally controlled potentio- meters (XDCP monolithic CMOS integrated circuit. The digitally controlled potentiometers are imple mented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. ...
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... X9251UB24I 50k Ω X9251UB24I-2.7 100k Ω X9251TS24 100k Ω X9251TS24-2.7 100k Ω X9251TS24I 100k Ω X9251TS24I-2.7 100k Ω X9251TV24 100k Ω X9251TV24-2.7 100k Ω X9251TV24I 100k Ω X9251TV24I-2.7 100k Ω X9251TB24 100k Ω X9251TB24-2.7 100k Ω X9251TB24I 100k Ω ...
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... X9251 CIRCUIT LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • ...
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... X9251 PIN CONFIGURATION SOIC/TSSOP X9251 PIN ASSIGNMENTS Pin Pin (SOIC) (CSP ...
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... A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1-A0 must be tie to a logic level which specify the internal address of the device, see Figures and 6. ...
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... X9251 PRINCIPLES OF OPERATION The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fi ...
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... Data Register zero (DR#0) upon power-up. (See Figure 1.) The wiper counter register is a volatile register; that is, its contents are lost when the X9251 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR# ...
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... I B DENTIFICATION YTE The first byte sent to the X9251 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the Identification Byte are a Device Type Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to Table 3). ...
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... X9251 Table 5. Instruction Set Instruction I3 Read Wiper Counter 1 Register Write Wiper Counter 1 Register Read Data Register 1 Write Data Register 1 XFR Data Register to 1 Wiper Counter Register XFR Wiper Counter 1 Register to Data Register Global XFR Data Registers 0 to Wiper Counter Registers Global XFR Wiper Counter ...
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... Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9251; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: REV 1.3.3 2/10/04 – ...
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... X9251 Figure 2. Two-Byte Instruction Sequence CS SCK ID3 ID2 ID1 ID0 Device ID Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case CS SCK ID3 ID2 ID1 ID0 0 0 Device ID Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case CS SCK ...
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... X9251 Figure 5. Three-Byte Instruction Sequence (Read Status Register) CS SCK ID3 ID2 ID1 ID0 0 0 Internal Device ID Address Figure 6. Increment/Decrement Instruction Sequence CS SCK ID3 ID2 ID1 ID0 0 0 Device ID Internal Address Figure 7. Increment/Decrement Timing Spec SCK ...
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... WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). REV 1.3.3 2/10/04 Instruction WCR Opcode Addresses (Sent by X9251 on SO ...
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... Opcode Addresses Rising Edge 0 Instruction DR and WCR CS Opcode Addresses Rising Edge 0 Instruction WCR Increment/Decrement Opcode Addresses (Sent by Master on SI) Instruction WCR Opcode Addresses (Sent by X9251 on SO) 0 www.xicor.com HIGH-VOLTAGE WRITE CYCLE HIGH-VOLTAGE WRITE CYCLE CS Rising Edge . . . . I/D I/D Data Byte CS Rising Edge WIP Characteristics subject to change without notice ...
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... X9251-2.7 Limits Min. Typ. 100 50 Pin -120 0.4 -1 -0.6 ±300 TOTAL -20 10/10/25 , and www.xicor.com Supply Voltage (V 5V ±10% X9251 2.7V to 5.5V Max. Units Test Conditions kΩ T version kΩ U version ± 25°C, each pot ±3 mA Ω 300 V TOTAL Ω ...
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... X9251 D.C. OPERATING CHARACTERISTICS Symbol Parameter I V supply current CC1 CC (active supply current CC2 CC (non-volatile write current (standby Input leakage current LI I Output leakage current LO V Input HIGH voltage IH V Input LOW voltage IL V Output LOW voltage OL V Output HIGH voltage ...
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... X9251 EQUIVALENT A.C. LOAD CIRCUIT V CC 2kΩ SO pin 2kΩ AC TIMING Symbol f SPI clock frequency SCK t SPI clock cycle rime CYC t SPI clock high rime WH t SPI clock low time WL t Lead time LEAD t Lag time LAG t SI, SCK, HOLD and CS input setup time ...
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... X9251 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol t High-voltage write cycle time (store instructions) WR XDCP TIMING Symbol t Wiper response time after the third (last) power supply is stable WRPO t Wiper response time after instruction issued (all load instructions) WRL SYMBOL TABLE . REV 1.3.3 2/10/04 Parameter Parameter ...
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... X9251 TIMING DIAGRAMS Input Timing CS t LEAD SCK MSB SI High Impedance SO Output Timing CS SCK t V MSB SO ADDR SI Hold Timing CS SCK HOLD REV 1.3.3 2/10/04 t CYC ... ... ... t HO ... t t HSU HH ... HOLD www.xicor.com LAG t RI ...
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... X9251 XDCP Timing (for All Load Instructions) CS SCK MSB SI VWx High Impedance SO Write Protect and Device Address Pins Timing REV 1.3.3 2/10/04 ... t WRL ... (Any Instruction WPASU WPAH www.xicor.com Characteristics subject to change without notice. LSB ...
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... X9251 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers V R Three terminal Potentiometer; Variable voltage divider Application Circuits Noninverting Amplifier – (1 Offset Voltage Adjustment 100KΩ – + TL072 10KΩ 10KΩ 10KΩ +12V -12V REV 1 ...
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... X9251 Application Circuits (continued) Attenuator – -1/2 ≤ G ≤ +1/2 Inverting Amplifier – Function Generator – + frequency ∝ amplitude ∝ REV 1.3.3 2/10/ 10kΩ ...
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... X9251 PACKAGING INFORMATION 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing Top View (Marking Side) Package Width Package Length Package Height Body Thickness Ball Height Ball Diameter Ball Pitch – Width Ball Pitch – Length Ball to Edge Spacing – Width Ball to Edge Spacing – ...
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... X9251 PACKAGING INFORMATION .026 (.65) BSC .303 (7.70) .311 (7.90) .0075 (.19) .0118 (.30) 0°–8° .020 (.50) .030 (.75) Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.3.3 2/10/04 24-Lead Plastic, TSSOP, Package Code V24 .169 (4.3) .252 (6.4) BSC .177 (4.5) .047 (1.20) .002 (.06) ...
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... X9251 PACKAGING INFORMATION Pin 1 Index (4X) 7° 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° – 8° 0.015 (0.40) 0.050 (1.27) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fi ...