X9252 Xicor, X9252 Datasheet
X9252
Available stocks
Related parts for X9252
X9252 Summary of contents
Page 1
... Low Power + Quad 256-tap + 2-Wire bus + Up/Down interface TM ) Potentiometer DESCRIPTION The X9252 integrates 4 digitally controlled potentio- meters (XDCP monolithic CMOS integrated circuit. The digitally controlled potentiometers are imple- mented using 255 resistive elements in a series array. Between each pair of elements are tap points con- nected to wiper terminals through switches ...
Page 2
... PIN CONFIGURATION ORDERING INFO Ordering Number X9252YV24-2.7 X9252YV24I-2.7 X9252WV24-2.7 X9252WV24I-2.7 X9252UV24-2.7 X9252UV24I-2.7 X9252TV24-2.7 X9252TV24I-2.7 REV 1.4.1 7/29/03 TSSOP 24 DS0 U X9252 RTOTAL Package 2.8k Ω ...
Page 3
... Device Address for 2-wire bus. Low terminal of DCP1. High terminal of DCP1. Wiper terminal DCP1. System ground Chip select for Up/Down interface. Wiper terminal of DCP2. High terminal of DCP2. Low terminal of DCP2. Serial Clock for 2-wire bus. DCP select for Up/Down interface. www.xicor.com X9252 ...
Page 4
... Supply Voltage (V CC 2.7V to 5.5V Test Conditions versions respectively % 25°C, each DCP % See test circuit Ω Wiper current = R TOTAL V Ref: 1kHz % (3) (3) V(R )=V(R )=V(R )=V V(R )=V(R )=V(R )=V See equivalent circuit Voltage at pin from X9252 (4) ) Limits )= )= ...
Page 5
... (for 2-Wire, Standby State only) CC Voltage at pin from 3mA OL Units Data changes per bit Years Max. Units Test Conditions OUT Units 0 0.9 CC 10ns V x 0.5 CC and 100 X9252 ; SDA = = ...
Page 6
... F HIGH LOW t SU:DAT t HD:DAT Clk 1 t SU:WP www.xicor.com Min. Max. 400 600 1300 600 600 600 100 30 300 300 0 1200 600 600 BUF STOP t HD:WP X9252 Units kHz µ SU:STO ...
Page 7
... SCL t ID U/D DS0, DS1 REV 1.4.1 7/29/03 Min. 600 600 600 2.5 2 CPHS t DI (3) MI www.xicor.com X9252 Limits Units (4) Typ. Max µs µs µs ms µs 100 500 µs µs 500 µs t CPHNS 90% 90% 10 ...
Page 8
... Equivalent Circuit R TOTAL www.xicor.com Typ. Max Min. Max )–V(R W(n)(actual) W(n)(expected) )–(V MI)]/MI , with n from 0 to 254 W(n+1) W(n) 6 (T1–T2 with T1 & T2 being 2 temperatures, and pin on power up X9252 Units ms Units µs )]/ ...
Page 9
... The Address inputs are used to set the least significant 3 bits of the 8-bit 2-wire interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the X9252. A maximum of 8 devices may occupy the 2-wire serial bus ...
Page 10
... Resistor Array – Up/Down Interface – 2-wire Interface Resistor Array Description The X9252 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical ...
Page 11
... Status Register must be both “0”, which is their power up default value. Other combinations are reserved and must not be used. The system may select the X9252, move the wiper, and deselect the device without having to store the lat- est wiper position in nonvolatile memory. After the ...
Page 12
... Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 2. On power up of the X9252, the SDA pin is in the input mode. Serial Start Condition ...
Page 13
... SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state www.xicor.com X9252 9 ACK ...
Page 14
... Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence is correctly issued (including the final STOP condition), the X9252 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, any Read or Write command is ignored by the X9252. Write Acknowledge Polling is used to determine whether a high voltage write cycle is completed. During acknowledge polling, the master fi ...
Page 15
... WCRs can be updated in a single serial write (see “Page Write Operation” on page 17), as well as all four registers of a given page in the DR array. The unique feature of the X9252 device is that writing or reading to a Data Register of a given DCP automati- cally updates/moves the WCR of that DCP with the content of the DR. In this manner data can be moved from a particular DCP register to that DCP’ ...
Page 16
... ACK. The master then terminates the transfer by generating a STOP condition. At this time, if the write operation volatile register (WCR, or SR), the X9252 is ready for the next read or write operation. If the write operation nonvolatile register (DR), and the WP pin is high, the X9252 begins the internal write cycle to the nonvolatile memory ...
Page 17
... Figure 7). After the receipt of each byte, the X9252 responds with an ACK, and the internal DCP address counter is incremented by one. The page address remains Figure 7 ...
Page 18
... START, the Slave Address byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to “1”. After each of the three bytes, the X9252 responds with an ACK. Then the X9252 transmits Data Figure 8. Move/Read Sequence ...
Page 19
... R I Two terminal Variable Resistor; Variable current Voltage Regulator V 317 adj (REG) = 1.25V (1 adj 2 V – /( (max /( (min X9252 (REG ...
Page 20
... www.xicor.com Filter – 1/(2πRC) Equivalent L-R Circuit – Leq >> – + X9252 ...
Page 21
... Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .002 (.06) .005 (.15) .010 (.25) Gage Plane Seating Plane .020 (.50) (1.78) .030 (.75) Detail A (20X) (0.42) .031 (.80) .041 (1.05) www.xicor.com (4.16) (7.72) (0.65) ALL MEASUREMENTS ARE TYPICAL ©Xicor, Inc. 2003 Patents Pending Characteristics subject to change without notice. X9252 ...