X9259 Xicor, X9259 Datasheet - Page 7

• Manufacturer Part Number: X9259
• Description: Quad Digitally-Controlled (XDCP) Potentiometers
• Manufacturer: Xicor

X9259
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9259
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9259 is still busy with the write operation no ACK
will be returned. If the X9259 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
REV 1.2.3 4/30/02
Command Completed
EnterACK Polling
Nonvolatile Write
Issue Slave
Operation?
Instruction
Returned?
START
Address
Proceed
Further
Issue
Issue
ACK
Yes
Yes
No
No
Issue STOP
Issue STOP
Proceed
www.xicor.com
INSTRUCTION AND REGISTER DESCRIPTION
Instructions
D
The first byte sent to the X9259 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9259; this is fixed
as 0101[B] (refer to Table 1).
The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3-A0 input pins. The slave address is
externally specified by the user. The X9259 compares
the serial data stream with the address input state; a
successful compare of both address bits is required
for the X9259 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3-A0 inputs
can be actively driven by CMOS input signals or tied
to V
I
The next byte sent to the X9259 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four data registers of each associated XDCP. The least
two significant bits point to one of four Wiper Counter
Registers or Pots. The format is shown in Table 2.
Register Selection
NSTRUCTION
EVICE
Register Selected
CC
A
or V
DDRESSING
DR0
DR1
DR2
DR3
B
SS
YTE
.
(I)
: I
Characteristics subject to change without notice.
DENTIFICATION
B
RB
0
0
1
1
YTE
(ID
AND
A)
RA
0
1
0
1
7 of 25