X9110 Xicor, X9110 Datasheet - Page 7

• Manufacturer Part Number: X9110
• Description: Single Digitally-Controlled (XDCP) Potentiometer
• Manufacturer: Xicor

Figure 2. Two-Byte Instruction Sequence
X9110 – Preliminary Information
Five of the seven instructions are four bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
– Write Wiper Counter Register – change current
– Read Data Register – read the contents of the
– Write Data Register – write a new value to the
– Read Status – This command returns the contents
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
between the potentiometer and one of its associated
registers. The Read Status Register instruction is the
only unique format (see Figure 4).
Two instructions require a two-byte sequence to
complete (see Figure 2). These instructions transfer
REV 1.1.4 11/13/00
wiper position of the selected pot,
wiper position of the selected pot,
selected data register;
selected data register.
of the WIP bit which indicates if the internal write
cycle is in progress.
WR
SCK
CS
SI
to complete. The transfer can occur
ID3 ID2 ID1 ID0
0
Device ID
1
0
WRL
1
. A transfer
0
0
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0
0
Internal
Address
A0
R/W
data between the host and the X9110; either between
the host and one of the Data Registers or directly
between the host and the Wiper Counter Register.
These instructions are:
– XFR Data Register to Wiper Counter Register –
– XFR Wiper Counter Register to Data Register –
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command (see
Figure 4).
Power Up and Down Requirements
At all times, the V+ voltage must be greater than or
equal to the voltage at R
or R
V-. During power up and power down, V
must reach their final values within 1msec of each
other.
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
I2
Instruction
Opcode
L
I1
must be greater than or equal to the voltage at
I0
0
Register
Address
Characteristics subject to change without notice.
RB RA
H
or R
0
0
L
0
0
, and the voltage at R
CC
, V+, and V-
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H