CAT5411BI-00-TE13 Catalyst Semiconductor, CAT5411BI-00-TE13 Datasheet - Page 8

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CAT5411BI-00-TE13

Manufacturer Part Number
CAT5411BI-00-TE13
Description
Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and SPI Interface
Manufacturer
Catalyst Semiconductor
Datasheet
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a
device type identifier. These bits for the CAT5411 are
fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address byte,
A1 - A0, are the internal slave address and must match
the physical device address which is defined by the state
of the A1 - A0 input pins for the CAT5411 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address
sent by the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to V
address byte must be set to 0.
Document No. 2114, Rev. F
CC
or V
(MSB)
(MSB)
ID3
0
SS
I3
. The remaining two bits in the device
ID2
1
I2
Device Type
Identifier
Instruction
Opcode
ID1
0
I1
ID0
1
I0
8
The next byte sent to the CAT5411 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format
is shown in Table 2.
0
R1
Data Register
Selection
DR0
DR1
DR2
DR3
0
R0
Slave Address
A1
WCR/Pot Selection
0
0
0
1
1
(LSB)
(LSB)
A0
P0
0
1
0
1

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