SAA7740 Philips Semiconductors, SAA7740 Datasheet - Page 12

• Manufacturer Part Number: SAA7740
• Description: Digital Audio Processing IC DAPIC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The SAA7740H is used as a slave device. The internal
operation is automatically synchronized with the word
select clock of the incoming data (I
an input frame of data, at f
to compute a stereo output sample. The external clock
therefore, should be minimum 384f
which generate more than 384 clocks cycles will cause the
processor to return to a wait state.
The external clock can be either a crystal connected
directly to the DAPIC, or any clock generated in the system
which contains DAPIC.
The I
Two I
DAPIC. The serial clock (DIBCK and DOBCK) and the
word select (DIWS and DOWS) are applied from an
external source. The two inputs and outputs are fully
synchronized. However, the inputs do not have to be
synchronized with the outputs. The clock and word select
signals can be separated at the input and output.
The input and output buses support word lengths in
accordance with the I
bits can be read by the DAPIC. Zeros will be added at the
LSB position should less than 20 bits be applied. If more
than 20 bits are applied the extra LSBs will be ignored.
The stereo word rate (f
Because the DAPIC is a slave device it can only be
connected to a master I
(see Chapter “Timing characteristics” and Fig.9).
I
The I
the DAPIC for the audio signal processing and write the
coefficients and the external delay line addresses of the
different signal processing algorithms. New coefficients
are updated in real time to the internal RAM.
Table 1
Note
1. AS1 and AS2 are the hardware (pin) programmable address bits. When the device detects this address it will
1997 May 30
2
C-bus control (SCL and SDA)
Digital Audio Processing IC (DAPIC)
respond with an acknowledge pulse on the SDA line.
BIT 7
2
2
2
C-bus interface is used to control the operation of
S-bus
S-bus inputs and outputs are available on the
0
I
2
C-bus slave address.
BIT 6
2
0
S-bus standard. Up to 20 significant
as
2
) can be either 32, 44.1 or 48 kHz.
S-bus transmitter or receiver
as
, 384 clock cycles are needed
BIT 5
2
as
S-bus format). Within
1
. External clocks
BIT 4
1
12
The transfer byte organization is as follows:
The first byte is the address of the I
addressed. If the device detects its address it answers with
an acknowledge by pulling down the data line (SDA) for
one clock period (SCL line). The second byte contains the
address of the internal RAM to which the first new
coefficient should have written. The data will then be
transmitted. Each new word (coefficient) is 2 bytes wide.
Up to four words of data can be written within one transfer.
Should the mode of the feature register be addressed then
only one data word will be transferred.
Because the I
bus, the clock has to be generated by the host
microcontroller.
The minimum time interval between two I
(bus free between a STOP and START condition) should
be:
Where:
START condition
First byte (8 bits)
Acknowledge (1-bit)
Second byte (8 bits)
Acknowledge (1-bit)
Third to tenth byte (8 bits)
Acknowledge (1-bit)
STOP condition.
Number of coefficients = coeff
Frequency f
BIT 3
t
inv
0
coeff
----------------------- - ms
2
as
f
C-bus (on the DAPIC) is a slave receiver
as
should be in kHz.
+
AS2
BIT 2
1
(1)
AS1
BIT 1
2
C-bus device being
(1)
Product specification
SAA7740H
2
C-bus transfers
BIT 0
0