SAA7740 Philips Semiconductors, SAA7740 Datasheet - Page 14

• Manufacturer Part Number: SAA7740
• Description: Digital Audio Processing IC DAPIC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
DRAM interface
The DRAM interface contains a nibble wide data bus, a
9-bit wide address bus and all necessary control signals to
enable the different DRAM configurations.
Timing of the control signals RAS, CAS, CAS2, A8B, OE
and WE is related to the applied clock frequency of the
DAPIC. The important timing parameters are the page
mode cycle time (t
refreshing rate and the maximum value for RAS to CAS
delay time (t
characteristics” and Fig.10). A read/write operation will
always be executed in the page mode (one row address
and four column addresses) because every data transfer
consists of 4 nibbles.
The refresh time of the DRAM (t
where ‘addr’ is the number of physical address lines and
f
1997 May 30
t
as
rfsh
Digital Audio Processing IC (DAPIC)
is measured in kHz.
2
------------ - ms
3f
addr
as
dRAS;CAS
cy;CAS
) (see Chapter “Timing
), the access time (t
rfsh
) must be greater than;
acc;RAS
), the
14
For fast DRAMs, the maximum value for RAS to CAS
delay time (t
Different DRAM combinations can be connected to the
DAPIC. The smallest DRAM is a 64
RAM. For this configuration, 16K data words can be
stored. When this RAM is connected to the DAPIC, the
MSB address signal (A8) can be felt floating.
The DAPIC can address up to 1 Mbit DRAMs. However,
RAMs greater than 1 Mbit can also be connected. This,
therefore, implies that the redundant address lines of the
RAM must be fixed to V
one of the other address pins.
The choice of a 256 kbit or a 1 Mbit DRAM device must be
indicated by a flag bit residing in the start address control
word of the different delay lines.
dRAS;CAS
) is important.
DD
or V
SS
or must be joined with
Product specification
4-bit (256 kbits)
SAA7740H