UPD703039 NEC, UPD703039 Datasheet
UPD703039
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UPD703039 Summary of contents
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... I/O lines Total: 151 The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y { PWM output: 4 channels { Vsync/Hsync separation circuit { On-chip key return function { On-chip clock generator { Power saving function: HALT/IDLE/STOP modes { ROM correction: 4 points changeable { Package: 176-pin plastic ...
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... P190 41 P191 42 P192 43 P193 44 Notes 1. Connect directly to V SS. 2. SCL0, SCL1, SDA0, and SDA1 are valid for the PD703039Y, 703040Y, and 703041Y only. 24 mm) Preliminary Data Sheet U13953EJ1V0DS00 132 P87/ANI15 131 P86/ANI14 130 P85/ANI13 129 P84/ANI12 128 P83/ANI11 ...
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... Clock Output (divided) CSYNCIN: Csync Input DSTB: Data Strobe HLDAK: Hold Acknowledge HLDRQ: Hold Request HSOUT0, HSOUT1: Hsync Output IC: Internally Connected INTCP80 to INTPC83,: Interrupt Request from Peripherals INTCP90 to INTCP93, INTP0 to INTP6, INTTCLR8, INTTI8, INTTI9 KR0 to KR7: Key Return LBEN: Lower Byte Enable NMI: ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y INTERNAL BLOCK DIAGRAM NMI INTP0 to INTP6 INTC INTCP80 to INTCP83, INTCP90 to INTCP93 INTTCLR8 INTTI8, INTTI9 Timer/counter TI000, TI001, 16-bit timers TI010, TI011 : TM0, TM1 TO0, TO1 8-bit timers TO80, TO81 : ...
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... PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 1. PIN FUNCTIONS .................................................................................................................................. 7 1.1 Port Pins .................................................................................................................................................... 7 1.2 Non-Port Pins........................................................................................................................................... 11 1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins ....................... 14 2. ELECTRICAL SPECIFICATIONS...................................................................................................... 18 3. PACKAGE DRAWING ....................................................................................................................... 37 4. RECOMMENDED SOLDERING CONDITIONS................................................................................ 38 6 CONTENTS Preliminary Data Sheet U13953EJ1V0DS00 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 1. PIN FUNCTIONS 1.1 Port Pins Pin Name I/O PULL P00 I/O Yes Port 0 8-bit I/O port P01 Input/output mode can be specified in 1-bit units. P02 P03 P04 P05 P06 P07 P10 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Pin Name I/O PULL P45 I/O No Port 4 8-bit I/O port P46 Input/output mode can be specified in 1-bit units. P47 P50 I/O No Port 5 8-bit I/O port P51 Input/output mode can ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Pin Name I/O PULL P94 I/O No Port 9 7-bit I/O port P95 Input/output mode can be specified in 1-bit units. P96 P100 I/O Yes Port 10 8-bit I/O port P101 Input/output mode can ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Pin Name I/O PULL P150 I/O No Port 15 8-bit I/O port P151 Input/output mode can be specified in 1-bit units. P152 P153 P154 P155 P156 P157 P160 I/O No Port 16 8-bit I/O ...
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... Bus hold request input HSOUT0 Output No Hsync signal output before revision HSOUT1 Hsync signal output after revision IC – – Internal connection (connect directly to V INTCP80 to Input No External capture input for CC80 to CC83 INTCP83 INTCP90 to Input No External capture input for CP90 to CP93 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Pin Name I/O PULL INTTCLR8 Input No External interrupt request input (digital noise elimination) INTTI8 Input No INTTI9 KR0 to KR7 Input Yes Key return input LBEN Output No Lower byte enable signal output ...
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... WRH Output No Higher byte write strobe signal output for external data bus WRL Lower byte write strobe signal output for external data bus X1 Input No Resonator connection for main system clock X2 – XT1 Input No Resonator connection for subsystem clock XT2 – Remark ...
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... PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins Table 1-1 shows the I/O circuit type of each pin and the recommended connection of unused pins. For the input/output configuration of each type, refer to Figure 1-1. Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (1/2) ...
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... PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (2/2) Pin Alternate Function P121 SO4 P122 SCK4 P123 CLO P124 TI6/TO6 P125 TI7/TO7 P126 TI10/TO10 P127 TI11/TO11 P130 to P133 INTCP80 to INTCP83 P134 TI8/INTTI8 P135 TCLR8/INTTCLR8 P136, P137 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Figure 1-1. Pin Input/Output Circuits (1/2) Type P-ch IN N-ch Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Push-pull output that can ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Figure 1-1. Pin Input/Output Circuits (2/2) Type 5 Pullup P-ch enable V DD Data P-ch Output N-ch disable Input enable Type 9 P-ch Comparator IN + – N-ch V (Threshold voltage) REF ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25° Parameter Symbol Supply voltage Input voltage Clock input voltage ...
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... Ports 7, 8 (includes alternate function pins sure not to exceed each absolute maximum rating (MAX.). Cautions 1. Do not directly connect to each other output pins (or I/O pins products, and do not connect them directly to V pins can be directly connected to each other. Moreover, external circuits that implement a timing that avoids conflict with the output of pins that go into high-impedance can be directly connected ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Recommended Oscillator (1) Main System Clock Oscillator (T A Parameter Symbol Oscillation frequency f XX Oscillation stabilization After reset release time After STOP mode release Note Values vary depending on the settings of the ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y DC Characteristics (T = –40 to +85° Parameter Symbol Input voltage, high V Pins in Note 1 , WAIT IH1 V Pins in Note 2 IH2 V Pins in Note 3, RESET ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Data Retention Characteristics (T = –40 to +85° Parameter Symbol Data retention voltage V Data retention current Supply voltage rising time Supply voltage falling time Supply voltage hold time (from STOP mode ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y AC Characteristics AC Test Input Waveforms ( Test Output Test Point ( Load ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Clock Timing Operating Conditions (T = –40 to +85° Parameter X1 input cycle t XT1 input cycle X1 input high-level width t XT1 input high-level width X1 input low-level width t XT1 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Bus Timing (CLKOUT Asynchronous –40 to +85° Parameter Address setup time (to ASTB ) Address hold time (from ASTB ) Address float from ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Bus Timing (CLKOUT Synchronous –40 to +85° Parameter Address delay time from CLKOUT Address float delay time from CLKOUT ASTB delay time from ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait) T1 CLKOUT (output) <39> A16 to A21 (output), Note AD0 to AD15 (I/O) <41> <11> ASTB (output) <22> DSTB (output), RD (output) WAIT (input) Note R/W (output), UBEN ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait) T1 CLKOUT (output) <39> A16 to A21 (output), Note AD0 to AD15 (I/O) <41> <11> ASTB (output) <22> DSTB (output), WRL (output), WRH (output) WAIT (input) Note R/W ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Bus Hold CLKOUT (output) <48> <49> HLDRQ (input) HLDAK (output) A16 to A21 (output), Note AD0 to AD15 (I/O) ASTB (output) DSTB (output), RD (output), WRL (output), WRH (output) Note R/W (output), UBEN (output), ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Reset/Interrupt Timing (T = –40 to +85° Parameter Symbol RESET high-level width t WRSH RESET low-level width t WRSL NMI high-level width t WNIH NMI low-level width t WNIL INTPn high-level width ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y TIn Input Timing (T = –40 to +85° Parameter Symbol TIn0, TIn1 (n = 00, 01) t TIH high-level width TIn ( 10, 11) high-level width TIn0, TIn1 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 3-Wire SIO Timing (1) Master Mode (T = –40 to +85° Parameter SCKn cycle time SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 3-Wire Variable-Length CSI Timing (1) Master Mode (T = –40 to +85° Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width SI4 setup time (to SCK4 ) SI4 hold time (from ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y UART Timing (T = –40 to +85° Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Remark ASCKn (input) Remark ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Bus Mode (Only for PD703039Y, 703040Y, and 703041Y –40 to +85° Parameter SCLn clock frequency f CLK Bus free time ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Bus Mode (Only for PD703039Y, 703040Y, and 703041Y) <77> <82> SCLn <80> <76> SDAn <75> Stop Start condition condition Remark A/D Converter (T = –40 to +85°C, ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y 3. PACKAGE DRAWING 176-PIN PLASTIC LQFP (FINE PITCH) (24x24 132 133 176 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum ...
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... For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions PD703039GM- ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y [MEMO] Preliminary Data Sheet U13953EJ1V0DS00 39 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y [MEMO] 40 Preliminary Data Sheet U13953EJ1V0DS00 ...
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PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y [MEMO] Preliminary Data Sheet U13953EJ1V0DS00 41 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • ...
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... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...