CS4228A-KS Cirrus Logic, CS4228A-KS Datasheet - Page 14

• Manufacturer Part Number: CS4228A-KS
• Description: 24-Bit/ 96 kHz Surround Sound Codec
• Manufacturer: Cirrus Logic

Each output can be independently muted via mute
control bits MUT6-1 in the DAC Mute1 Control
register. When asserted, MUT attenuates the corre-
sponding DAC to its maximum value (90.5 dB).
When MUT is deasserted, the corresponding DAC
returns to the attenuation level set in the Digital
Volume Control register. The attenuation is
ramped up and down at the rate specified by the
RMP1:0 bits.
To achieve complete digital attenuation of an in-
coming signal, Hard Mute controls are provided.
When asserted, Hard Mute will send zero data to a
corresponding pair of DACs. Hard Mute is not
ramped, so it should only be asserted after setting
the two corresponding MUT bits to prevent high
frequency transients from appearing on the DAC
outputs. Hard Mute is controlled by the
HMUTE56/34/12 bits in the DAC Mute2 Control
register.
3.4 Mute Control
The Mute Control pin is typically connected to an
external mute control circuit as shown in Figure 7
and Figure 8. The Mute Control pin is asserted dur-
ing power up, power down, and when serial port
clock errors are present. The pin can also be con-
trolled by the user via the control port, or automat-
ically asserted when zero data is present on all six
DAC inputs. To prevent large transients on the out-
put, it is desirable to mute the DAC outputs before
the Mute Control pin is asserted. Please see the
MUTEC pin in the Pin Descriptions section for
more information.
3.5 Clock Generation
The master clock, MCLK, is supplied to the
CS4228A from an external clock source. If MCLK
stops for 10 µs, the CS4228A will enter Power
Down Mode in which the supply current is reduced
as specified under “Power Supply”. In all modes it
is required that the number of MCLK periods per
SCLK and LRCK period be constant.
14
3.5.1 Clock Source
The CS4228A internal logic requires an external
master clock, MCLK, that operates at multiples of
the sample rate frequency, Fs. The MCLK/Fs ratio
is determined by the CI1:0 bits in the CODEC
Clock Mode register.
3.5.2 Synchronization
The serial port is internally synchronized with
MCLK. If from one LRCK cycle to the next, the
number of MCLK cycles per LRCK cycle changes
by more than 32, the CS4228A will undergo an in-
ternal reset of its data paths in an attempt to resyn-
chronize. Consequently, it is advisable to mute the
DACs and clear the DIGPDN bit when changing
from one clock source to another to avoid the out-
put of undesirable audio signals as the device re-
synchronizes. It is adviseable to ensure that MCLK
complies with the Switching Characteristics at all
times when switching clock sources without reset-
ting the part.
3.6 Digital Interfaces
3.6.1 Serial Audio Interface Signals
The serial audio data is presented in 2's comple-
ment binary form with the MSB first in all formats.
The serial interface clock, SCLK, is used for both
transmitting and receiving audio data. SCLK can
be generated by the CS4228A (master mode) or it
can be input from an external source (slave mode).
Mode selection is made with the DMS1:0 bits in
the Serial Port Mode register. The number of
SCLK cycles in one sample period can be set using
the DCK1:0 bits as detailed in the Serial Port Mode
register.
The Left/Right clock (LRCK) is used to indicate
left and right data frames and the start of a new
sample period. It may be an output of the CS4228A
(master mode), or it may be generated by an exter-
nal source (slave mode). The frequency of LRCK is
the same as the system sample rate, Fs.
CS4228A
DS511PP1