LTC4258 LINER [Linear Technology], LTC4258 Datasheet - Page 7

• Manufacturer Part Number: LTC4258
• Description: Quad IEEE 802.3af Power over Ethernet Controller with Integrated Detection
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
RESET (Pin 1): Chip Reset, Active Low. When the RESET
pin is low, the LTC4258 is held inactive with all ports off
and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4258 begins normal
operation. RESET can be connected to an external capaci-
tor or RC network to provide a power turn-on delay.
Internal filtering of the RESET pin prevents glitches less
than 1 s wide from resetting the LTC4258. Pull RESET
high with 10k or tie to V
BYP (Pin 2): Bypass Output. The BYP pin is used to
connect the internally generated – 20V supply to an exter-
nal 0.1 F bypass capacitor. Use a 100V rated 0.1 F, X7R
capacitor. Do not connect the BYP pin to any other external
circuitry.
INT (Pin 3): Interrupt Output, Open Drain. INT will pull low
when any one of several events occur in the LTC4258. It
will return to a high impedance state when bits 6 or 7 are
set in the Reset PB register (1Ah). The INT signal can be
used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See Register Functions and Applications
Information for more information. The INT pin is only
updated between I
SCL (Pin 4): Serial Clock Input. High impedance clock
input for the I
be connected directly to the I
SDAOUT (Pin 5): Serial Data Output, Open Drain Data
Output for the I
two pins to implement the bidirectional SDA function to
simplify optoisolation of the I
dard bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
SDAIN (Pin 6): Serial Data Input. High impedance data input
for the I
to implement the bidirectional SDA function to simplify
optoisolation of the I
bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
U
2
C serial interface bus. The LTC4258 uses two pins
U
2
C serial interface bus. The SCL pin should
2
C Serial Interface Bus. The LTC4258 uses
2
C transactions.
U
2
C bus. To implement a standard
DD
.
2
2
C bus. To implement a stan-
C SCL bus line.
AD3 (Pin 7): Address Bit 3. Tie the address pins high or low
to set the I
sponds. This address will be (010A
high or low with 10k or tie to V
AD2 (Pin 8): Address Bit 2. See AD3.
AD1 (Pin 9): Address Bit 1. See AD3.
AD0 (Pin 10): Address Bit 0. See AD3.
DETECT1 (Pin 11): Detect Sense, Port 1. The LTC4258
Powered Device (PD) detection, classification and AC
disconnect hardware monitors port 1 with this pin. Con-
nect DETECT1 to the output port via a low leakage diode
(see Figure 1).
DETECT2 (Pin 12): Detection Sense, Port 2. See DETECT1.
DETECT3 (Pin 13): Detection Sense, Port 3. See DETECT1.
DETECT4 (Pin 14): Detection Sense, Port 4. See DETECT1.
DGND (Pin 15): Digital Ground. DGND should be con-
nected to the return from the 3.3V supply. DGND and
AGND should be tied together.
V
power supply relative to DGND. V
DGND near the LTC4258 with at least a 0.1 F capacitor.
SHDN1 (Pin 17): Shutdown Port 1, Active Low. When
pulled low, SHDN1 shuts down port 1, regardless of the
state of the internal registers. Pulling SHDN1 low is
equivalent to setting the Reset Port 1 bit in the Reset
Pushbutton register (1Ah). Internal filtering of the SHDN1
pin prevents glitches less than 1 s wide from reseting the
LTC4258. Pull SHDN1 high with 10k or tie to V
SHDN2 (Pin 18): Shutdown Port 2, Active Low. See
SHDN1.
SHDN3 (Pin 19): Shutdown Port 3, Active Low. See
SHDN1.
SHDN4 (Pin 20): Shutdown Port 4, Active Low. See
SHDN1.
DD
(Pin 16): Logic Power Supply. Connect to a 3.3V
2
C serial address to which the LTC4258 re-
DD
DD
or DGND.
3
must be bypassed to
A
2
LTC4258
A
1
A
0
)
b
. Pull AD3
DD
.
4258p
7