ICS1574BEB ICST [Integrated Circuit Systems], ICS1574BEB Datasheet
ICS1574BEB
Related parts for ICS1574BEB
ICS1574BEB Summary of contents
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Integrated Circuit Systems, Inc. User Programmable Laser Engine Pixel Clock Generator Description The ICS1574B is a very high performance monolithic phase- locked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed- mode technology, the ICS1574B ...
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ICS1574B Pin Configuration (Do Not Connect) Pin Descriptions ...
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PCLK Programmable Divider The ICS1574B has a programmable divider (referred to in Fig- ure 1 as the PCLK divider) that is used to generate the PCLK clock frequency for the pixel clock output. The modulus of this divider may be ...
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ICS1574B PLL Post-Scaler A programmable post-scaler may be inserted between the VCO and the PCLK divider of the ICS1574B. This is useful in generating lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler is not affected ...
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Reference Oscillator and Crystal Selection The ICS1574B has circuitry on-board to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal anti- (also called parallel-) resonant mode. See the AC ...
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ICS1574B Power Supplies and Decoupling The ICS1574B has two VSS pins to reduce the effects of package inductance. Both pins are connected to the same potential on the die (the ground bus). BOTH of these pins should connect to the ...
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Register Mapping — ICS1574B NOTE not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to automatically generate all register values based on requirements. Contact factory for details. BIT(S) ...
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ICS1574B BIT(S) BIT REF. 15 Reserved 16 AUX_PCLK When in the AUX-EN test mode, this bit controls the 17 – 24 Reserved 25 – 27 V[0]..V[2] 28 Reserved 29 – 30 P[0]..P[1] 31 Reserved 32 P[2] See text. 33 – ...
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BIT(S) BIT REF. 45 Reserved 46 PCLK_EN 47, 48 Reserved 49 – 55 R[0]..R[6] 56 REF_POL DESCRIPTION Must be set to 1. Must be set to 0. Disables the PCLK divider when set to 1 regardless of PCLKEN input state. ...
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ICS1574B Table 1 — "A" & "M" Divider Programming ...
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Absolute Maximum Ratings VDD, VDDO (measured to V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . V Digital Outputs . . . . ...
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... Ordering Information ICS1574BM / ICS1574BEB Example: ICS 1574B ...